SPRADN4B October   2024  – September 2025 AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 User's Guide Usage Guidelines
      1. 1.1.1 Custom Board Schematics Design Guidelines - References Used in the User's Guide
      2. 1.1.2 Processor Family-Specific User's Guide
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
        1. 1.1.4.1 Common Checklist for Use With All Schematic Design Guidelines and Schematics Review Sections
          1. 1.1.4.1.1 Custom Board Schematic Design Implementation Checklist Sub-Sections Description
      5. 1.1.5 FAQ Reference for User's Guide Usage During Schematic Self-review
    2. 1.2 AM62Px [AMH] Processor Family List of Processors
    3. 1.3 Updates to Schematics Design Guidelines and Schematics Review Checklist
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Referenced Collaterals During Custom Board Schematic Design
    2. 2.2 Hardware Design Considerations for Custom Board Design User's Guide
  6. 3 Processor-Specific Information
    1. 3.1 Selection of Processor OPN (Orderable Part Number)
    2. 3.2 Processor-specific Data Sheet Use Case and Version Referenced for User's Guide Edits
    3. 3.3 Peripheral Instance Naming Convention - Data Sheet and TRM
    4. 3.4 Processor Peripherals and IO Connection When Not Used
    5. 3.5 Ordering and Quality Information for AM62Px Processor Family
    6. 3.6 Checklist for Selection of Required Processor GPN (Generic Part Number) and OPN (Ordering Part Number)
  7. 4 Processor Power Architecture
    1. 4.1 Generating Processor-Specific and Peripherals (Attached Device) Supply Rails
      1. 4.1.1 AM62P, AM62P-Q1 Processor Family Power Architecture
        1. 4.1.1.1 Power Management IC (PMIC) Based Power Architecture
          1. 4.1.1.1.1 PMIC Based Power Architecture Checklist for TPS65224x
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power Devices (DC/DC, LDO) Based Power Architecture
          1. 4.1.1.2.1 Discrete DC/DCs
          2. 4.1.1.2.2 Discrete LDOs
          3. 4.1.1.2.3 Discrete Power Devices (DC/DC, LDO) Based Power Architecture Checklist
    2. 4.2 Processor Power Rails Supply Control, Sequencing and Supply Overload Protection
      1. 4.2.1 Load Switch (Processor Supply Rail Power Switching)
        1. 4.2.1.1 Load Switch (Processor Supply Rail Power Switching) Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
      1. 5.1.1 Evaluation Module (Starter Kit) Checklist
    2. 5.2 Processor-Specific SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Processor-specific Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs Protection - Provision for External ESD Protection Devices
        6. 5.2.1.6 Peripheral Clock Outputs Series Resistor
        7. 5.2.1.7 Peripheral Clock Outputs Pulldown Resistor
        8. 5.2.1.8 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding SK Design (Schematic, Board) and Reuse
        1. 5.2.2.1 Updated SK Schematic With Design, Review and CAD Notes Added
          1. 5.2.2.1.1 AM62P, AM62P-Q1 Processor Family
        2. 5.2.2.2 SK Design Files Reuse for Custom Board Design
          1. 5.2.2.2.1 SK Design Files Reuse for Custom Board Design - Checklist
      3. 5.2.3 SK Schematic Pages Sequencing (Based on Functions, Reuse) and SK Board Layout
    3. 5.3 Processor-Specific SDK
    4. 5.4 General Design Recommendations (to Know) Before Starting the Custom Board Design
      1. 5.4.1  Processor Documentation
      2. 5.4.2  Processor Pin Attributes (Pinout) Verification
      3. 5.4.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.4.4  RSVD Reserved Pins (Signals)
      5. 5.4.5  Note on PADCONFIG Registers
      6. 5.4.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.4.7  Pin Connectivity Requirements and Reference to Processor-Specific SK
      8. 5.4.8  Custom Board High-Speed Interface Design Guidelines
      9. 5.4.9  Recommendation for LVCMOS (GPIO) Output Current Source or Current Sink
      10. 5.4.10 Connection of Slow Ramp Signal (Input) or Capacitor Load (Output) to Processor IOs
      11. 5.4.11 Processor and Processor Peripherals Design Related Queries During Custom Board Design
      12. 5.4.12 General Design Recommendations (to Know) Before Starting the Custom Board Design Checklist
      13. 5.4.13 Attached Devices Recommendations
  9. 6 Processor-Specific Recommendations for Power, Clock, Reset, Boot and Debug
    1. 6.1 Common (Processor Start-Up) Connections
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Core and Peripherals Supplies
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 IO Supply for IO Groups
          1. 6.1.1.2.1 Additional Information
          2. 6.1.1.2.2 IO Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 Supply for VPP Checklist
        4. 6.1.1.4 Supply Connection for Partial IO (Low Power) Mode Configuration
          1. 6.1.1.4.1 Partial IO Mode Functionality
          2. 6.1.1.4.2 Partial IO Low Power Mode When Used
          3. 6.1.1.4.3 Partial IO Low Power Mode When Not Used
          4. 6.1.1.4.4 Processor-specific Data Sheet Reference for Power Sequence
          5. 6.1.1.4.5 Partial IO (Low Power) Mode Checklist
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62P, AM62P-Q1 Processor Family
        2. 6.1.2.2 Additional Information
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clocks (Inputs / Outputs)
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 MCU_OSC0 (High Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          2. 6.1.3.1.2 WKUP_LFOSC0 (Low Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to MAIN Domain)
          4. 6.1.3.1.4 Clock Input Checklist - MCU_OSC0
          5. 6.1.3.1.5 Clock Input Checklist - WKUP_LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Inputs Checklist
        5. 6.1.4.5 Processor Reset Status Outputs Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Configuration
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Custom Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG Interface and EMU Signals When Used
      2. 6.2.2 JTAG Interface and EMU Signals When Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Custom Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals Power, Interface and Connections
    1. 7.1 Supported Processor Cores and MCU Cores
    2. 7.2 Supply Connections for IO Supply for IO Groups
      1. 7.2.1 AM62P, AM62P-Q1 IO supply
      2. 7.2.2 Supply Connections for IO Supply for IO Groups Checklist
    3. 7.3 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD Card/SDIO), OSPI/QSPI and GPMC)
      1. 7.3.1 DDR Subsystem (DDRSS)
        1. 7.3.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.1.1 AM62P, AM62P-Q1 Processor Family
        2. 7.3.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.2.1 AM62P, AM62P-Q1 Processor Family
            1. 7.3.1.2.1.1 Memory Interface Configuration
            2. 7.3.1.2.1.2 Routing Topology and Connection of Memory Terminations
            3. 7.3.1.2.1.3 Resistors for DDRSS Control and Calibration
            4. 7.3.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.3.1.2.1.5 Data Bit or Byte Swapping
            6. 7.3.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.3.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.3.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.3.2.1.1 AM62P, AM62P-Q1 Processor Family
            1. 7.3.2.1.1.1 MMC0 Interface Used
              1. 7.3.2.1.1.1.1 IO Power Supply
              2. 7.3.2.1.1.1.2 eMMC Interface Signals Connection
              3. 7.3.2.1.1.1.3 eMMC (Attached Device) Reset
              4. 7.3.2.1.1.1.4 Capacitors for the Power Supply Rails
            2. 7.3.2.1.1.2 MMC0 Interface Not Used
            3. 7.3.2.1.1.3 MMC0 (eMMC) Checklist
          2. 7.3.2.1.2 Additional Information on eMMC PHY
          3. 7.3.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.3.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.3.2.2.1 IO Power Supply
          2. 7.3.2.2.2 Signals Connection
            1. 7.3.2.2.2.1 MMC1 Signals Used for SD Card Interface (Recommended)
            2. 7.3.2.2.2.2 MMC2 Signals Used for SD Card Interface
            3. 7.3.2.2.2.3 Additional Information
          3. 7.3.2.2.3 SD Card Power Supply Switch EN Reset Logic
          4. 7.3.2.2.4 External ESD Protection for the SD Card Interface Signals
          5. 7.3.2.2.5 Capacitors for the IO Supply for IO Groups Supply Rails
          6. 7.3.2.2.6 SD Card Interface (MMC1) Checklist
        3. 7.3.2.3 MMC1/MMC2 SDIO (Embedded) Interface
          1. 7.3.2.3.1 IO Power Supply
          2. 7.3.2.3.2 Signals Connection
          3. 7.3.2.3.3 SDIO (MMC2 Recommended, Embedded) Interface Checklist
        4. 7.3.2.4 Additional Information
      3. 7.3.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.3.3.1 IO Power Supply
        2. 7.3.3.2 Signals Connection
        3. 7.3.3.3 OSPI/QSPI Device Reset
        4. 7.3.3.4 Loopback Clock
        5. 7.3.3.5 Interface to Multiple (Attached) Devices
        6. 7.3.3.6 Capacitors for the Power Supply Rails
        7. 7.3.3.7 OSPI0 or QSPI0 Peripheral Interface Implementation Checklist
      4. 7.3.4 General-Purpose Memory Controller (GPMC)
        1. 7.3.4.1 IO Power Supply
        2. 7.3.4.2 GPMC Interface
        3. 7.3.4.3 Signals Connection
          1. 7.3.4.3.1 GPMC NAND
        4. 7.3.4.4 Memory (Attached Device) Reset
        5. 7.3.4.5 Capacitors for the Power Supply Rails
        6. 7.3.4.6 GPMC Interface Checklist
    4. 7.4 External Communication Interface (Ethernet (CPSW3G0), USB2.0, UART and MCAN)
      1. 7.4.1 Ethernet (MAC) Interface
        1. 7.4.1.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
          1. 7.4.1.1.1  IO Power Supply
          2. 7.4.1.1.2  MAC (Data, Control and Clock) Interface Signals Connection
          3. 7.4.1.1.3  EPHy Reset
          4. 7.4.1.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
            1. 7.4.1.1.4.1 Crystal Used as Clock Source for Processor and EPHy
            2. 7.4.1.1.4.2 External Oscillator Used as Clock Source
            3. 7.4.1.1.4.3 Processor Clock Output (CLKOUT0)
          5. 7.4.1.1.5  Ethernet PHY Pin Strapping
          6. 7.4.1.1.6  External Interrupt (EXTINTn)
            1. 7.4.1.1.6.1 External Interrupt (EXTINTn) Checklist
          7. 7.4.1.1.7  MAC (Media Access Controller) to MAC Interface
          8. 7.4.1.1.8  MDIO (Management Data Input/Output) Interface
          9. 7.4.1.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
          10. 7.4.1.1.10 Capacitors for the Power Supply Rails
          11. 7.4.1.1.11 Ethernet Interface Checklist
      2. 7.4.2 Universal Serial Bus (USB2.0)
        1. 7.4.2.1 USBn (n = 0-1) Interface When Used
          1. 7.4.2.1.1 USB Interface Configured as Host
          2. 7.4.2.1.2 USB Interface Configured as Device
          3. 7.4.2.1.3 USB Interface Configured as Dual-Role-Device
          4. 7.4.2.1.4 USB Type-C
        2. 7.4.2.2 USBn (n = 0-1) Interface When Not Used
        3. 7.4.2.3 Additional Information
        4. 7.4.2.4 USB Interface Checklist
      3. 7.4.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.4.3.1 UART Interface When Not Used
        2. 7.4.3.2 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.4.4 Modular Controller Area Network (MCAN) with Full CAN-FD Support
        1. 7.4.4.1 Modular Controller Area Network Checklist
    5. 7.5 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.5.1 Multichannel Serial Peripheral Interface (MCSPI) and Audio Peripheral - Multichannel Audio Serial Port (MCASP)
        1. 7.5.1.1 Connection of MCSPI and MCASP Interface Signals
        2. 7.5.1.2 MCSPI Interface Checklist
        3. 7.5.1.3 MCASP Interface Checklist
      2. 7.5.2 Inter-Integrated Circuit (I2C)
        1. 7.5.2.1 I2C Interface Signals Connection
        2. 7.5.2.2 I2C (Open-drain Output Type IO Buffer) Interface Checklist
        3. 7.5.2.3 I2C (Emulated Open-drain Output Type IO) Interface Checklist
    6. 7.6 User Interface (CSIRX0, DPI, OLDI0, DSI), GPIO and Hardware Diagnostics
      1. 7.6.1 Camera Serial Interface (CSI-RX, CSI-2, CSIRX0)
        1. 7.6.1.1 CSIRX0 Peripheral When Used
        2. 7.6.1.2 CSIRX0 Peripheral When Not Used
        3. 7.6.1.3 CSIRX0 Peripheral Checklist
      2. 7.6.2 Display Subsystem (DSS)
        1. 7.6.2.1 Display Parallel Interface (DPI)
          1. 7.6.2.1.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.1.1.1 IO Power Supply
            2. 7.6.2.1.1.2 Connection
            3. 7.6.2.1.1.3 DPI (Attached Device) Reset
            4. 7.6.2.1.1.4 DPI Signals Connection
            5. 7.6.2.1.1.5 Capacitors for the Power Supply Rail
            6. 7.6.2.1.1.6 DPI (VOUT0) Peripheral Checklist
        2. 7.6.2.2 Open LVDS Display Interface (OLDI0)
          1. 7.6.2.2.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.2.1.1 OLDI0 Display Interface Used
              1. 7.6.2.2.1.1.1 OLDI0 Interface Compatibility
              2. 7.6.2.2.1.1.2 IO Power Supply
              3. 7.6.2.2.1.1.3 OLDI0 (Attached Device) Reset
              4. 7.6.2.2.1.1.4 Capacitors for the Power Supply Rail
            2. 7.6.2.2.1.2 OLDI0 Peripheral Not Used
            3. 7.6.2.2.1.3 Additional Information
            4. 7.6.2.2.1.4 OLDI0 Peripheral Checklist
        3. 7.6.2.3 Display Serial Interface (DSI)
          1. 7.6.2.3.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.3.1.1 DSITX0 Peripheral Used
              1. 7.6.2.3.1.1.1 DSITX0 Peripheral Checklist
            2. 7.6.2.3.1.2 DSITX0 Peripheral Not Used
      3. 7.6.3 General Purpose Input/Output (GPIO)
        1. 7.6.3.1 Availability of CLKOUT on Processor GPIO
        2. 7.6.3.2 GPIO Connection and Addition of External Buffer
        3. 7.6.3.3 Additional Information
        4. 7.6.3.4 GPIO Checklist
      4. 7.6.4 On-board Hardware Diagnostics
        1. 7.6.4.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.6.4.1.1 Voltage Monitor Inputs Connection When Used
            1. 7.6.4.1.1.1 Voltage Monitor Checklist
          2. 7.6.4.1.2 Voltage Monitor Inputs Connection When Not Used
        2. 7.6.4.2 Internal Temperature Monitoring
          1. 7.6.4.2.1 Internal Temperature Monitoring Checklist
        3. 7.6.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.6.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
          1. 7.6.4.4.1 Crystal or External Oscillator Mal-function
    7. 7.7 SK Specific Circuit Implementation (Reuse)
    8. 7.8 Performing Board Level Testing During Custom Board Bring-up
      1. 7.8.1 Processor Pin Configuration Using PinMux Tool
      2. 7.8.2 Schematics Configurations
      3. 7.8.3 Connection of Supply Rails to External Pullups
      4. 7.8.4 Peripheral (Subsystem) Clock Outputs
      5. 7.8.5 General Board Bring-up and Debug
        1. 7.8.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.8.5.2 Additional Information
        3. 7.8.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of Custom Board Schematic Design
  12. 9 Custom Board Layout Notes (Added Near to the Schematic Sections) and General Guidelines
    1. 9.1 Layout Considerations
  13. 10Custom Board Design Simulation
    1. 10.1 DDR-MARGIN-FW
  14. 11Additional References
    1. 11.1 FAQs Covering AM64x, AM243x, AM62x, AM62Ax, AM62D-Q1, AM62Px, AM62Lx Processor Families
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Schematics Review (Self) and Schematic Review Request (Suppliers)
    4. 11.4 Processor Attached Devices Checklist
  15. 12User's Guide Content and Usage Summary
  16. 13References
    1. 13.1  AM62P, AM62P-Q1
    2. 13.2  AM62L
    3. 13.3  AM62A7, AM62A3, AM62A7-Q1, AM62A3-Q1, AM62A1-Q1
    4. 13.4  AM62D-Q1
    5. 13.5  AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP
    6. 13.6  Common for all Processor Families
    7. 13.7  Master List of Available FAQs - Processor Family Wise
    8. 13.8  Master List of Available FAQs - Sitara Processor Families
    9. 13.9  FAQs Including Software Related
    10. 13.10 FAQs for Attached Devices
  17. 14Terminology
  18. 15Revision History
7.4.1.1.11 Ethernet Interface Checklist

General

Review and verify the following for the custom schematic design:

  1. Reviewed above "Common checklist for all sections" section of the user's guide.
  2. MAC interface configuration - RGMII or RMII.
  3. IO level compatibility between processor MAC interface signals and EPHY (attached device).
  4. Matching of processor and EPHY clock specifications.
  5. Clocking of EPHy and processor MAC for RMII interface.
  6. MAC-to-MAC interface connections.
  7. MDIO interface and EPHY address configuration.
  8. Implementation of EPHY reset logic.
  9. Implementation of x2 EPHy reset logic.
  10. Pullup on the MDIO interface MDC (clock signal) can be optional (EPHY can have internal pulldown; the recommendation is to verify the availability of pull in the EPHY data sheet).

Schematic Review

Follow the list below for the custom schematic design:

  1. The recommendation is to compare the bulk and decoupling capacitors used for process and the EPHy supply rails with SK schematic implementation (when TI EPHY is used).
  2. The recommendation is to provision for a series resistors (on the TDx signals near to processor MAC TDx output pins).
  3. The recommendation is to verify the attached device IO supply and the IO supply for IO group VDDSHV2 referenced by (powered by) the processor MAC interface signals are connected to the same supply source and follow the ROC.
  4. MDIO interface connection including pullup (2.2kΩ (Follow EPHY recommendations)) for MDIO data signal added near to the EPHY. MDIO connection to multiple devices and the addition of pullup near each EPHY. When more than x1 EPHY are used, configuration of EPHY address for MDIO interface.
  5. A crystal with internal oscillator or an external oscillator for each EPHy or a common external oscillator with buffers (outputs are use case dependent) can be used.
  6. The recommendation is to match the EPHy and the processor clock specifications.
  7. Clocking of EPHy and processor MAC for RMII interface including addition of buffers (based on the EPHY configuration) and clock architecture (use of common Oscillator and Buffer with multiple outputs). In case processor clock output is connected to more than one input, each of the clock input is recommended to be the buffered output of the clock.
  8. When MAC-to-MAC interface is used, the recommendation is to verify IO level compatibility, fail-safe operation (when x2 processor MACs are referenced to (powered by) different power sources) and matching of clock specifications.
  9. The recommendation is to verify the EPHY reset implementation including ANDing logic, AND gate input pullup and EPHY reset input pull with the SK implementation when TI EPHY is used. A 3-input ANDing logic can be used to implement the attached device (EPHY) reset. Processor GPIO (used to locally reset the EPHY) is connected as one of the input to the ANDing logic AND gate with provision for pullup (to support boot) near to the ANDing logic AND gate input and provision for 0Ω to isolate the GPIO output for testing or debug. The other two inputs to the AND gate are the MAIN domain POR (cold reset) status output (PORz_OUT) and MAIN domain warm reset status output (RESETSTATz).
  10. When more than one (x2) EPHy are used, the recommendation is to provide provision to reset the EPHy individually.

Additional

  1. The recommendation is to follow the steps below recommended when TI EPHY is used:
    • Obtain a review of the implementation done with the EPHY business unit or product line.
    • The recommendation is to verify recommended bulk and decoupling capacitors are added and the power sequence requirements are followed.
    • The recommendation is to verify RBIAS resistor value & tolerance, selection of the RJ45 connector, external ESD protection provision for MDI signals and connection of RJ45 connector shield to circuit ground
  2. A single channel (with single input and single output) buffers, or single input with dual or multiple output buffer can be used to connect the clock output of the oscillator to the processor and EPHy. For a specific use case (requirement for some of the industrial applications using a Time Sensitive Networking (TSN)), single input and two or more output (based on number of EPHy used) buffer is recommended for the processor and the EPHy.
  3. When EPHY is configured as RMII peripheral, a single input (common clock input), two-output phase aligned buffer is recommended.
  4. Consider adding 0Ω (optional and recommended when space is not a constraint) series resistors near to the attached device (EPHY) for the RDx signals.
  5. To optimize the ANDing logic, it is ok to use a dual input AND gate with RESETSTATz and the processor GPIO as inputs. ANDing logic additionally performs IO level translation. The recommendation is to verify the reset IO level compatibility before optimizing the reset ANDing logic. IO level mismatch can cause supply leakage and affect board performance.
  6. In case Ethernet boot is considered, the recommendation is to review the silicon errata, verify the supported EPHY interface configurations, MAC interface port used versus recommended, and the recommended clock and interface connection.