SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

47.5.2 SSI_REGS Registers

Table 47-3 lists the memory-mapped registers for the SSI_REGS registers. All register offset addresses not listed in Table 47-3 should be considered as reserved locations and the register contents should not be modified.

Table 47-3 SSI_REGS Registers

Offset	Acronym	Register Name	Section
0h	SSICR0	SSI Control 0	Go
4h	SSICR1	SSI Control 1	Go
8h	SSIDR	SSI Data	Go
Ch	SSISR	SSI Status	Go
10h	SSICPSR	SSI Clock Prescale	Go
14h	SSIIM	SSI Interrupt Mask	Go
18h	SSIRIS	SSI Raw Interrupt Status	Go
1Ch	SSIMIS	SSI Masked Interrupt Status	Go
20h	SSIICR	SSI Interrupt Clear	Go
24h	SSIDMACTL	SSI DMA Control	Go
FB0h	SSIPV	SSI Peripheral Version	Go
FC0h	SSIPP	SSI Peripheral Properties	Go
FC4h	SSIPC	SSI Peripheral Configuration	Go
FD0h	SSIPeriphID4	SSI Peripheral Identification 4	Go
FD4h	SSIPeriphID5	SSI Peripheral Identification 5	Go
FD8h	SSIPeriphID6	SSI Peripheral Identification 6	Go
FDCh	SSIPeriphID7	SSI Peripheral Identification 7	Go
FE0h	SSIPeriphID0	SSI Peripheral Identification 0	Go
FE4h	SSIPeriphID1	SSI Peripheral Identification 1	Go
FE8h	SSIPeriphID2	SSI Peripheral Identification 2	Go
FECh	SSIPeriphID3	SSI Peripheral Identification 3	Go
FF0h	SSIPCellID0	SSI PrimeCell Identification 0	Go
FF4h	SSIPCellID1	SSI PrimeCell Identification 1	Go
FF8h	SSIPCellID2	SSI PrimeCell Identification 2	Go
FFCh	SSIPCellID3	SSI PrimeCell Identification 3	Go

Complex bit access types are encoded to fit into small table cells. Table 47-4 shows the codes that are used for access types in this section.

Table 47-4 SSI_REGS Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

47.5.2.1 SSICR0 Register (Offset = 0h) [Reset = 00000000h]

SSICR0 is shown in Figure 47-10 and described in Table 47-5.

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SSI Control 0

Figure 47-10 SSICR0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCR								SPH	SPO	FRF		DSS
R/W-0h								R/W-0h	R/W-0h	R/W-0h		R/W-0h

Table 47-5 SSICR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	SCR	R/W	0h	SSI Serial Clock Rate This bit field is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=SysClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. Reset type: PER.RESET
7	SPH	R/W	0h	SSI Serial clock PHase This bit is only applicable to the Freescale SPI Format.The control bit selects the clock edge that captures data and allows it to change state. This bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. SPH Value Description 0 Data is captured on the first clock edge transition. 1 Data is captured on the second clock edge transition. Reset type: PER.RESET
6	SPO	R/W	0h	SSI Serial clock POlarity Value Description 0 A steady state Low value is placed on the pin SSInClk when data is not being transferred. 1 A steady state High value is placed on the pin SSInClk when data is not being transferred. Reset type: PER.RESET
5-4	FRF	R/W	0h	SSI FRame Format Select Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Synchronous Serial Frame Format Texas Instruments 0x2 Reserved 0x3 Reserved Reset type: PER.RESET
3-0	DSS	R/W	0h	SSI Data Size Select Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data Reset type: PER.RESET

47.5.2.2 SSICR1 Register (Offset = 4h) [Reset = 00000000h]

SSICR1 is shown in Figure 47-11 and described in Table 47-6.

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SSI Control 1

Figure 47-11 SSICR1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED			RESERVED	RESERVED	FSSHLDFRM	HSCLKEN	DIR
R-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED	EOT	RESERVED	MS	SSE	LBM
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 47-6 SSICR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	FSSHLDFRM	R/W	0h	FSS Hold Frame Value Description 0 Pulse SSInFss at every byte (the bit DSS in the SSICR0 register must be set to 0x7 (data size 8 bits) in thisconfiguration) 1 Hold SSInFss for the whole frame Reset type: PER.RESET
9	HSCLKEN	R/W	0h	High Speed Clock Enable High speed clock enable is available only when operating as a master. Value Description 0 Use Input Clock 1 Use High Speed Clock Note: For proper functionality of high speed mode, the HSCLKEN bit in the SSICR1 register should be set before any SSI data transfer or after applying a reset to the QSSI module. In addition, the SSE bit must be set to 0x1 before the HSCLKEN bit is set. Reset type: PER.RESET
8	DIR	R/W	0h	SSI Direction of Operation Value Description 0 TX (Transmit Mode) write direction 1 RX (Receive Mode) read direction Reset type: PER.RESET
7-6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	EOT	R/W	0h	End of Transmission This bit is only valid for Master mode devices and operations ( =0x0).MS Value Description 0 The TXRIS interrupt indicates that the transmit FIFO is half full or less. 1 The End of Transmit interrupt mode for the TXRIS interrupt is enabled.When using uDMA, the DMATX bit cannot be set to 1 in any mode. If used with uDMA, it prevents RISEOT from asserting. If the bit is kept at 0 during operation, an interrupt is still generated when the TX FIFO is half or less full with or without using the uDMA.EOT (Legacy) Reset type: PER.RESET
3	RESERVED	R/W	0h	Reserved
2	MS	R/W	0h	SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when the SSI is disabled (SSE=0). Value Description 0 The SSI is configured as a master. 1 The SSI is configured as a slave. Reset type: PER.RESET
1	SSE	R/W	0h	SSI Synchronous Serial Port Enable Value Description 0 SSI operation is disabled. 1 SSI operation is enabled. This bit must be cleared before any control registers are reprogrammed. The bit HSCLKEN in the SSICR1 register should be set only after applying reset to the QSSI module and enabling the QSSI by setting the SSE bit, and before any SSI data transfer. All other bits in the SSICR1 register and all bits in SSICR0 register can only be programmed when the SSE is clear. Reset type: PER.RESET
0	LBM	R/W	0h	SSI Loopback Mode Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. Reset type: PER.RESET

47.5.2.3 SSIDR Register (Offset = 8h) [Reset = 00000000h]

SSIDR is shown in Figure 47-12 and described in Table 47-7.

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SSI Data

Figure 47-12 SSIDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																DATA
R-0h																R/W-0h

Table 47-7 SSIDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	DATA	R/W	0h	SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO.Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. Reset type: PER.RESET

47.5.2.4 SSISR Register (Offset = Ch) [Reset = 00000003h]

SSISR is shown in Figure 47-13 and described in Table 47-8.

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SSI Status

Figure 47-13 SSISR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											BSY	RFF	RNE	TNF	TFE
R-0h											R-0h	R-0h	R-0h	R-1h	R-1h

Table 47-8 SSISR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	BSY	R	0h	SSI Busy Bit Value Description 0 The SSI is idle. 1 The SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. Reset type: PER.RESET
3	RFF	R	0h	SSI Receive FIFO Full Value Description 0 The receive FIFO is not full. 1 The receive FIFO is full. Reset type: PER.RESET
2	RNE	R	0h	SSI Receive FIFO Not Empty Value Description 0 The receive FIFO is empty. 1 The receive FIFO is not empty. Reset type: PER.RESET
1	TNF	R	1h	SSI Transmit FIFO Not Full Value Description 0 The transmit FIFO is full. 1 The transmit FIFO is not full. Reset type: PER.RESET
0	TFE	R	1h	SSI Transmit FIFO Empty Value Description 0 The transmit FIFO is not empty. 1 The transmit FIFO is empty. Reset type: PER.RESET

47.5.2.5 SSICPSR Register (Offset = 10h) [Reset = 00000000h]

SSICPSR is shown in Figure 47-14 and described in Table 47-9.

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SSI Clock Prescale

Figure 47-14 SSICPSR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CPSDVSR
R-0h																								R/W-0h

Table 47-9 SSICPSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CPSDVSR	R/W	0h	SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSInClk. The LSB always returns 0 on reads. Reset type: PER.RESET

47.5.2.6 SSIIM Register (Offset = 14h) [Reset = 00000000h]

SSIIM is shown in Figure 47-15 and described in Table 47-10.

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SSI Interrupt Mask

Figure 47-15 SSIIM Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	EOTIM	DMATXIM	DMARXIM	TXIM	RXIM	RTIM	RORIM
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 47-10 SSIIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	EOTIM	R/W	0h	End of Transmit Interrupt Mask Value Description 0 The end of transmit interrupt is masked. 1 The end of transmit interrupt is not masked. Reset type: PER.RESET
5	DMATXIM	R/W	0h	SSI Transmit DMA Interrupt Mask Value Description 0 The transmit DMA interrupt is masked. 1 The transmit DMA interrupt is not masked. Reset type: PER.RESET
4	DMARXIM	R/W	0h	SSI Receive DMA Interrupt Mask Value Description 0 The receive DMA interrupt is masked. 1 The receive DMA interrupt is not masked. Reset type: PER.RESET
3	TXIM	R/W	0h	SSI Transmit FIFO Interrupt Mask Value Description 0 The transmit FIFO interrupt is masked. 1 The transmit FIFO interrupt is not masked. Reset type: PER.RESET
2	RXIM	R/W	0h	SSI Receive FIFO Interrupt Mask Value Description 0 The receive FIFO interrupt is masked. 1 The receive FIFO interrupt is not masked. Reset type: PER.RESET
1	RTIM	R/W	0h	SSI Receive Time-Out Interrupt Mask Value Description 0 The receive FIFO time-out interrupt is masked. 1 The receive FIFO time-out interrupt is not masked. Reset type: PER.RESET
0	RORIM	R/W	0h	SSI Receive Overrun Interrupt Mask Value Description 0 The receive FIFO overrun interrupt is masked. 1 The receive FIFO overrun interrupt is not masked. Reset type: PER.RESET

47.5.2.7 SSIRIS Register (Offset = 18h) [Reset = 00000008h]

SSIRIS is shown in Figure 47-16 and described in Table 47-11.

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SSI Raw Interrupt Status

Figure 47-16 SSIRIS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	EOTRIS	DMATXRIS	DMARXRIS	TXRIS	RXRIS	RTRIS	RORRIS
R-0h	R-0h	R-0h	R-0h	R-1h	R-0h	R-0h	R-0h

Table 47-11 SSIRIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	EOTRIS	R	0h	End of Transmit Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit FIFO is empty, and the last bit has been transmitted out of the serializer.This bit is cleared when a 1 is written to the EOTIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
5	DMATXRIS	R	0h	SSI Transmit DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit DMA has completed.This bit is cleared when a 1 is written to the DMATXIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
4	DMARXRIS	R	0h	SSI Receive DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The receive DMA has completed.This bit is cleared when a 1 is written to the DMARXIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
3	TXRIS	R	1h	SSI Transmit FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit FIFO is half empty or less. If the EOT bit in the SSICR1 register is clear, If the EOT bit is set, the transmit FIFO is empty, and the last bit has been transmitted out of the serializer.This bit is cleared when the transmit FIFO is more than half full. (if the EOT bit is clear) or when it has any data in it (if the EOT bit is set) Reset type: PER.RESET
2	RXRIS	R	0h	SSI Receive FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO is half full or more.This bit is cleared when the receive FIFO is less than half full. Reset type: PER.RESET
1	RTRIS	R	0h	SSI Receive Time-Out Raw Interrupt Status Value Description 0 No interrupt. 1 The receive time-out has occurred.This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
0	RORRIS	R	0h	SSI Receive Overrun Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO has overflowed. This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET

47.5.2.8 SSIMIS Register (Offset = 1Ch) [Reset = 00000000h]

SSIMIS is shown in Figure 47-17 and described in Table 47-12.

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SSI Masked Interrupt Status

Figure 47-17 SSIMIS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	EOTMIS	DMATXMIS	DMARXMIS	TXMIS	RXMIS	RTMIS	RORMIS
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 47-12 SSIMIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	EOTMIS	R	0h	End of Transmit Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the transmission of the last data bit.This bit is cleared when a 1 is written to the EOTIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
5	DMATXMIS	R	0h	SSI Transmit DMA Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due tothe completion of the transmit DMA.This bit is cleared when a 1 is written to the DMATXIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
4	DMARXMIS	R	0h	SSI Receive DMA Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the completion of the receive DMA.This bit is cleared when a 1 is written to the DMARXIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
3	TXMIS	R	0h	SSI Transmit FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the transmit FIFO being half empty or less. (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set)This bit is cleared when the transmit FIFO is more than half empty .(if the EOT bit is clear) or when it has any data in it (if the EOT bit is set) Reset type: PER.RESET
2	RXMIS	R	0h	SSI Receive FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO being half full or more.This bit is cleared when the receive FIFO is less than half full. Reset type: PER.RESET
1	RTMIS	R	0h	SSI Receive Time-Out Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive time out.This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET
0	RORMIS	R	0h	SSI Receive Overrun Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO overflowing.This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. Reset type: PER.RESET

47.5.2.9 SSIICR Register (Offset = 20h) [Reset = 00000000h]

SSIICR is shown in Figure 47-18 and described in Table 47-13.

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SSI Interrupt Clear

Figure 47-18 SSIICR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	EOTIC	DMATXIC	DMARXIC	RESERVED		RTIC	RORIC
R-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0h		R-0/W1S-0h	R-0/W1S-0h

Table 47-13 SSIICR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	EOTIC	R-0/W1S	0h	End of Transmit Interrupt Clear Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register and the EOTMIS bit in the SSIMIS register. Reset type: PER.RESET
5	DMATXIC	R-0/W1S	0h	SSI Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the SSIRIS register and the DMATXMIS bit in the SSIMIS register. Reset type: PER.RESET
4	DMARXIC	R-0/W1S	0h	SSI Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the SSIRIS register and the DMARXMIS bit in the SSIMIS register. Reset type: PER.RESET
3-2	RESERVED	R	0h	Reserved
1	RTIC	R-0/W1S	0h	SSI Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and the RTMIS bit in the SSIMIS register. Reset type: PER.RESET
0	RORIC	R-0/W1S	0h	SSI Receive Overrun Interrupt Clear Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and the RORMIS bit in the SSIMIS register. Reset type: PER.RESET

47.5.2.10 SSIDMACTL Register (Offset = 24h) [Reset = 00000000h]

SSIDMACTL is shown in Figure 47-19 and described in Table 47-14.

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SSI DMA Control

Figure 47-19 SSIDMACTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						TXDMAE	RXDMAE
R-0h						R/W-0h	R/W-0h

Table 47-14 SSIDMACTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	TXDMAE	R/W	0h	Transmit DMA Enable Value Description 0 uDMA for the transmit FIFO is disabled. 1 uDMA for the transmit FIFO is enabled. Reset type: PER.RESET
0	RXDMAE	R/W	0h	Receive DMA Enable Value Description 0 uDMA for the receive FIFO is disabled. 1 uDMA for the receive FIFO is enabled. Reset type: PER.RESET

47.5.2.11 SSIPV Register (Offset = FB0h) [Reset = 00000400h]

SSIPV is shown in Figure 47-20 and described in Table 47-15.

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SSI Peripheral Version

Figure 47-20 SSIPV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																MAJOR								MINOR
R-0h																R-4h								R-0h

Table 47-15 SSIPV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	MAJOR	R	4h	Major Revision This field specifies the major revision number of the module. Corresponds to the IP version used on Snowflake. Reset type: PER.RESET
7-0	MINOR	R	0h	Minor Revision This field specifies the minor revision number of the module. Corresponds to the IP version used on Snowflake. Reset type: PER.RESET

47.5.2.12 SSIPP Register (Offset = FC0h) [Reset = 00000009h]

SSIPP is shown in Figure 47-21 and described in Table 47-16.

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SSI Peripheral Properties

Figure 47-21 SSIPP Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	FSSHLDFRM	MODE		HSCLK
R-0h			R-0h	R-1h	R-0h		R-1h

Table 47-16 SSIPP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	FSSHLDFRM	R	1h	SSInFss Hold Frame Capability Value Description 0 Hold Frame capability disabled.SSInFss 1 Hold Frame capability enabled.SSinFss Reset type: PER.RESET
2-1	MODE	R	0h	Mode of Operation Indicates what SSI functionality is supported. Value Description 0x0 Legacy SSI mode Others reserved Reset type: PER.RESET
0	HSCLK	R	1h	High Speed Capability Value Description 0 High Speed clock capability disabled. 1 High speed clock capability enabled. Reset type: PER.RESET

47.5.2.13 SSIPC Register (Offset = FC4h) [Reset = 00000000h]

SSIPC is shown in Figure 47-22 and described in Table 47-17.

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SSI Peripheral Configuration

Figure 47-22 SSIPC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 47-17 SSIPC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

47.5.2.14 SSIPeriphID4 Register (Offset = FD0h) [Reset = 00000000h]

SSIPeriphID4 is shown in Figure 47-23 and described in Table 47-18.

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SSI Peripheral Identification 4

Figure 47-23 SSIPeriphID4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID4
R-0h																								R-0h

Table 47-18 SSIPeriphID4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID4	R	0h	SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.15 SSIPeriphID5 Register (Offset = FD4h) [Reset = 00000000h]

SSIPeriphID5 is shown in Figure 47-24 and described in Table 47-19.

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SSI Peripheral Identification 5

Figure 47-24 SSIPeriphID5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID5
R-0h																								R-0h

Table 47-19 SSIPeriphID5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID5	R	0h	SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.16 SSIPeriphID6 Register (Offset = FD8h) [Reset = 00000000h]

SSIPeriphID6 is shown in Figure 47-25 and described in Table 47-20.

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SSI Peripheral Identification 6

Figure 47-25 SSIPeriphID6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID6
R-0h																								R-0h

Table 47-20 SSIPeriphID6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID6	R	0h	SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.17 SSIPeriphID7 Register (Offset = FDCh) [Reset = 00000000h]

SSIPeriphID7 is shown in Figure 47-26 and described in Table 47-21.

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SSI Peripheral Identification 7

Figure 47-26 SSIPeriphID7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID7
R-0h																								R-0h

Table 47-21 SSIPeriphID7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID7	R	0h	SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.18 SSIPeriphID0 Register (Offset = FE0h) [Reset = 00000022h]

SSIPeriphID0 is shown in Figure 47-27 and described in Table 47-22.

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SSI Peripheral Identification 0

Figure 47-27 SSIPeriphID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID0
R-0h																								R-22h

Table 47-22 SSIPeriphID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID0	R	22h	SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.19 SSIPeriphID1 Register (Offset = FE4h) [Reset = 00000000h]

SSIPeriphID1 is shown in Figure 47-28 and described in Table 47-23.

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SSI Peripheral Identification 1

Figure 47-28 SSIPeriphID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID1
R-0h																								R-0h

Table 47-23 SSIPeriphID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID1	R	0h	SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.20 SSIPeriphID2 Register (Offset = FE8h) [Reset = 00000018h]

SSIPeriphID2 is shown in Figure 47-29 and described in Table 47-24.

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SSI Peripheral Identification 2

Figure 47-29 SSIPeriphID2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID2
R-0h																								R-18h

Table 47-24 SSIPeriphID2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID2	R	18h	SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.21 SSIPeriphID3 Register (Offset = FECh) [Reset = 00000001h]

SSIPeriphID3 is shown in Figure 47-30 and described in Table 47-25.

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SSI Peripheral Identification 3

Figure 47-30 SSIPeriphID3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								PID3
R-0h																								R-1h

Table 47-25 SSIPeriphID3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	PID3	R	1h	SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. Reset type: PER.RESET

47.5.2.22 SSIPCellID0 Register (Offset = FF0h) [Reset = 0000000Dh]

SSIPCellID0 is shown in Figure 47-31 and described in Table 47-26.

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SSI PrimeCell Identification 0

Figure 47-31 SSIPCellID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CID0
R-0h																								R-Dh

Table 47-26 SSIPCellID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CID0	R	Dh	SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. Reset type: PER.RESET

47.5.2.23 SSIPCellID1 Register (Offset = FF4h) [Reset = 000000F0h]

SSIPCellID1 is shown in Figure 47-32 and described in Table 47-27.

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SSI PrimeCell Identification 1

Figure 47-32 SSIPCellID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CID1
R-0h																								R-F0h

Table 47-27 SSIPCellID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CID1	R	F0h	SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. Reset type: PER.RESET

47.5.2.24 SSIPCellID2 Register (Offset = FF8h) [Reset = 00000005h]

SSIPCellID2 is shown in Figure 47-33 and described in Table 47-28.

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SSI PrimeCell Identification 2

Figure 47-33 SSIPCellID2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CID2
R-0h																								R-5h

Table 47-28 SSIPCellID2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CID2	R	5h	SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. Reset type: PER.RESET

47.5.2.25 SSIPCellID3 Register (Offset = FFCh) [Reset = 000000B1h]

SSIPCellID3 is shown in Figure 47-34 and described in Table 47-29.

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SSI PrimeCell Identification 3

Figure 47-34 SSIPCellID3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CID3
R-0h																								R-B1h

Table 47-29 SSIPCellID3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CID3	R	B1h	SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. Reset type: PER.RESET