SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

3.16.3 CLK_CFG_REGS Registers

Table 3-37 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses not listed in Table 3-37 should be considered as reserved locations and the register contents should not be modified.

Table 3-37 CLK_CFG_REGS Registers

Offset	Acronym	Register Name	Write Protection	Section
0h	CLKSEM	Clock Control Semaphore Register	EALLOW	Go
2h	CLKCFGLOCK1	Lock bit for CLKCFG registers	EALLOW	Go
8h	CLKSRCCTL1	Clock Source Control register-1	EALLOW	Go
Ah	CLKSRCCTL2	Clock Source Control register-2	EALLOW	Go
Ch	CLKSRCCTL3	Clock Source Control register-3	EALLOW	Go
Eh	SYSPLLCTL1	SYSPLL Control register-1	EALLOW	Go
14h	SYSPLLMULT	SYSPLL Multiplier register	EALLOW	Go
16h	SYSPLLSTS	SYSPLL Status register		Go
18h	AUXPLLCTL1	AUXPLL Control register-1	EALLOW	Go
1Eh	AUXPLLMULT	AUXPLL Multiplier register	EALLOW	Go
20h	AUXPLLSTS	AUXPLL Status register		Go
22h	SYSCLKDIVSEL	System Clock Divider Select register	EALLOW	Go
24h	AUXCLKDIVSEL	Auxillary Clock Divider Select register	EALLOW	Go
26h	PERCLKDIVSEL	Peripheral Clock Divider Selet register	EALLOW	Go
28h	XCLKOUTDIVSEL	XCLKOUT Divider Select register	EALLOW	Go
2Ah	CLBCLKCTL	CLB Clocking Control Register	EALLOW	Go
2Ch	LOSPCP	Low Speed Clock Source Prescalar	EALLOW	Go
2Eh	MCDCR	Missing Clock Detect Control Register	EALLOW	Go
30h	X1CNT	10-bit Counter on X1 Clock		Go
32h	XTALCR	XTAL Control Register	EALLOW	Go
36h	ETHERCATCLKCTL	ETHERCATCLKCTL	EALLOW	Go
38h	CMCLKCTL	CMCLKCTL	EALLOW	Go

Complex bit access types are encoded to fit into small table cells. Table 3-38 shows the codes that are used for access types in this section.

Table 3-38 CLK_CFG_REGS Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
WSonce	W Sonce	Write Set once
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.16.3.1 CLKSEM Register (Offset = 0h) [Reset = 00000000h]

CLKSEM is shown in Figure 3-39 and described in Table 3-39.

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Clock Control Semaphore Register

Figure 3-39 CLKSEM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY
R-0/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														SEM
R-0-0h														R/W-0h

Table 3-39 CLKSEM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	KEY	R-0/W	0h	Writing the value 0xa5a5 will allow the writing of the SEM bits, else writes are ignored. Reads will return 0. Note: [1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored Reset type: CPU1.SYSRSn
15-2	RESERVED	R-0	0h	Reserved
1-0	SEM	R/W	0h	This register provides a mechanism to acquire all the CLKCFG registers (except this register) by CPU1 or CPU2. A CPU can perform read/writes to any of the CLKCFG registers (except this register) only if it owns the semaphore. Otherwise, writes are ignored and reads will return 0x0. Semaphore State Transitions: A value of 00, 10, 11 gives ownership to CPU1 A value of 01 gives ownership to CPU2. The following are the only state transitions allowed on these bits. 00,11 <-> 01 (allowed by CPU2) 00,11 <-> 10 (allowed by CPU1) If a CPU doesn't own the CLK_CFG_REGS set of registers (as defined by the state of this semaphore), reads from that CPU to all those registers return 0x0 and writes are ignore. Note that this is not true of CLKSEM register. The CLKSEM register's reads and writes are always allowed from both CPU1 and CPU2. Reset type: CPU1.SYSRSn

3.16.3.2 CLKCFGLOCK1 Register (Offset = 2h) [Reset = 00000000h]

CLKCFGLOCK1 is shown in Figure 3-40 and described in Table 3-40.

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Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Figure 3-40 CLKCFGLOCK1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED					CMCLKCTL	ETHERCATCLKCTL	XTALCR
R-0-0h					R/WSonce-0h	R/WSonce-0h	R/WSonce-0h

15	14	13	12	11	10	9	8
LOSPCP	CLBCLKCTL	PERCLKDIVSEL	AUXCLKDIVSEL	SYSCLKDIVSEL	AUXPLLMULT	RESERVED	RESERVED
R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R-0-0h	R-0-0h

7	6	5	4	3	2	1	0
AUXPLLCTL1	SYSPLLMULT	SYSPLLCTL3	SYSPLLCTL2	SYSPLLCTL1	CLKSRCCTL3	CLKSRCCTL2	CLKSRCCTL1
R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h	R/WSonce-0h

Table 3-40 CLKCFGLOCK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R-0	0h	Reserved
18	CMCLKCTL	R/WSonce	0h	Lock bit for CMCLKCTL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
17	ETHERCATCLKCTL	R/WSonce	0h	Lock bit for ETHERCATCLKCTL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
16	XTALCR	R/WSonce	0h	Lock bit for XTALCR register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
15	LOSPCP	R/WSonce	0h	Lock bit for LOSPCP register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
14	CLBCLKCTL	R/WSonce	0h	Lock bit for CLBCLKCTL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
13	PERCLKDIVSEL	R/WSonce	0h	Lock bit for PERCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
12	AUXCLKDIVSEL	R/WSonce	0h	Lock bit for AUXCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
11	SYSCLKDIVSEL	R/WSonce	0h	Lock bit for SYSCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
10	AUXPLLMULT	R/WSonce	0h	Lock bit for AUXPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn
9	RESERVED	R-0	0h	Reserved
8	RESERVED	R-0	0h	Reserved
7	AUXPLLCTL1	R/WSonce	0h	Lock bit for AUXPLLCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
6	SYSPLLMULT	R/WSonce	0h	Lock bit for SYSPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
5	SYSPLLCTL3	R/WSonce	0h	Lock bit for SYSPLLCTL3 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
4	SYSPLLCTL2	R/WSonce	0h	Lock bit for SYSPLLCTL2 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
3	SYSPLLCTL1	R/WSonce	0h	Lock bit for SYSPLLCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
2	CLKSRCCTL3	R/WSonce	0h	Lock bit for CLKSRCCTL3 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
1	CLKSRCCTL2	R/WSonce	0h	Lock bit for CLKSRCCTL2 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn
0	CLKSRCCTL1	R/WSonce	0h	Lock bit for CLKSRCCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn

3.16.3.3 CLKSRCCTL1 Register (Offset = 8h) [Reset = 00000000h]

CLKSRCCTL1 is shown in Figure 3-41 and described in Table 3-41.

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Clock Source Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-41 CLKSRCCTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED	XTALOFF	INTOSC2OFF_NOTSUPPORTED	RESERVED	OSCCLKSRCSEL
R-0-0h		R/W-0h	R/W-0h	R/W-0h	R-0-0h	R/W-0h

Table 3-41 CLKSRCCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-6	RESERVED	R-0	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	XTALOFF	R/W	0h	Crystal (External) Oscillator Off Bit: This bit turns external oscillator off: 0 = Crystal (External) Oscillator On (default on reset) 1 = Crystal (External) Oscillator Off NOTE: Ensure no resources are using a clock source prior to disabling it. For example OSCCLKSRCSEL (SYSPLL), AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock), TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT). Reset type: XRSn
3	INTOSC2OFF_NOTSUPPORTED	R/W	0h	RESERVED: This bit is not supported any more, and should not be set to 1. Note: If this bit is set to 1 it will turn OFF INTOSC2 and lead to PLL failure Reset type: XRSn
2	RESERVED	R-0	0h	Reserved
1-0	OSCCLKSRCSEL	R/W	0h	Oscillator Clock Source Select Bit: This bit selects the source for OSCCLK. 00 = INTOSC2 (default on reset) 01 = External Oscillator (XTAL) 10 = INTOSC1 11 = reserved (default to INTOSC1) At power-up or after an XRSn, INTOSC2 is selected by default. Whenever the user changes the clock source using these bits, the SYSPLLMULT register will be forced to zero and the PLL will be bypassed and powered down. This prevents potential PLL overshoot. The user will then have to write to the SYSPLLMULT register to configure the appropriate multiplier. Notes: [1] Reserved selection defaults to 00 configuration [2] INTOSC1 is recommended to be used only after missing clock detection. If user wants to re-lock the PLL with INTOSC1 (the back-up clock source) after missing clock is detected, he can do a MCLKCLR and lock the PLL. [3] Any writes to this bit must be followed with at least 300 CPU Cycles of wait time by adding at least 300 NOP instructions. [4] Changing the OSCCLKSRC while PLL is running and used by system (i.e. PLLCLKEN=1), can lead to dead System Clock. User needs to first bypass the PLL clock from the system by PLLCLKEN=0, and then change the OSCCLK source. Reset type: XRSn

3.16.3.4 CLKSRCCTL2 Register (Offset = Ah) [Reset = 00000000h]

CLKSRCCTL2 is shown in Figure 3-42 and described in Table 3-42.

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Clock Source Control register-2
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-42 CLKSRCCTL2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED				MCANABITCLKSEL		RESERVED
R-0-0h				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CANBBCLKSEL		CANABCLKSEL		AUXOSCCLKSRCSEL
R/W-0h		R/W-0h		R/W-0h		R/W-0h

Table 3-42 CLKSRCCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-12	RESERVED	R-0	0h	Reserved
11-10	MCANABITCLKSEL	R/W	0h	MCAN Bit Clock Source Select Bit: 00 = CM.Perx.SYSCLK or CPU1.PERx.SYSCLK based on PALLOCATE.MCAN_A setting. 01 = AUXPLLRAWCLK 10 = AUXCLKIN 11 = Rsvd If bit timing clock source has to change, then PCLKCR bit for the corresponding MCAN instance has to be cleared to '0' first before updating the values in thies field. Once the value is updated, the corresponding PCLKCR bit of this instance can be set back to '1'. Reset type: XRSn
9-8	RESERVED	R/W	0h	Reserved
7-6	RESERVED	R/W	0h	Reserved
5-4	CANBBCLKSEL	R/W	0h	CANB Bit Clock Source Select Bit: 00 = CPUx.PERx.SYSCLK (default on reset), if PALLOCATE0.CANB is 0. Else CM.Perx.SYSCLK. 01 = External Oscillator (XTAL) 10 = AUXCLKIN (from GPIO) 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. If bit timing clock source has to change, then PCLKCR bit for the corresponding DCAN instance has to be cleared to '0' first before updating the values in thies field. Once the value is updated, the corresponding PCLKCR bit of this instance can be set back to '1'. Reset type: XRSn
3-2	CANABCLKSEL	R/W	0h	CANA Bit Clock Source Select Bit: 00 = PERx.SYSCLK (default on reset),if PALLOCATE0.CANA is 0 else CMCLK. 01 = External Oscillator (XTAL) 10 = AUXCLKIN (from GPIO) 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. If bit timing clock source has to change, then PCLKCR bit for the corresponding DCAN instance has to be cleared to '0' first before updating the values in thies field. Once the value is updated, the corresponding PCLKCR bit of this instance can be set back to '1'. Reset type: XRSn
1-0	AUXOSCCLKSRCSEL	R/W	0h	Oscillator Clock Source Select Bit: This bit selects the source for AUXOSCCLK: 00 = INTOSC2 (default on reset) 01 = External Oscillator (XTAL) 10 = AUXCLKIN (from GPIO) 11 = Reserved(default to INTOSC2) Whenever the user changes the clock source using these bits, the AUXPLLMULT register will be forced to zero. The user will then have to write to the AUXPLLMULT register to configure the appropriate multiplier. The user must wait 10 OSCCLK cycles before writing to AUXPLLMULT or disabling the previous clock source to allow the change to complete. The missing clock detection circuit does not affect these bits. Notes: [1] Changing the AUXOSCCLKSRC while PLL is running and AUXPLLCLKEN=1, can lead to dead AUXPLLCLK. User needs to first bypass the AUXPLL by AUXPLLCLKEN=0, and then change the AUXOSCCLK source. Reset type: XRSn

3.16.3.5 CLKSRCCTL3 Register (Offset = Ch) [Reset = 00000000h]

CLKSRCCTL3 is shown in Figure 3-43 and described in Table 3-43.

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Clock Source Control register-3
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-43 CLKSRCCTL3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												XCLKOUTSEL
R-0-0h												R/W-0h

Table 3-43 CLKSRCCTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-4	RESERVED	R-0	0h	Reserved
3-0	XCLKOUTSEL	R/W	0h	XCLKOUT Source Select Bit: This bit selects the source for XCLKOUT: 0000 = PLLSYSCLK (default on reset) 0001 = SYSPLLCLK 0010 = CPU1.SYSCLK 0011 = CPU2.SYSCLK 0100 = AUXPLLCLK 0101 = INTOSC1 0110 = INTOSC2 0111 = XTAL OSC o/p clock 1000 = CMCLK 1100 = PLLRAWCLK 1101 = AUXPLLRAWCLK others = Reserved Reset type: CPU1.SYSRSn

3.16.3.6 SYSPLLCTL1 Register (Offset = Eh) [Reset = 00000000h]

SYSPLLCTL1 is shown in Figure 3-44 and described in Table 3-44.

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SYSPLL Control register-1

Figure 3-44 SYSPLLCTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	RESERVED	RESERVED	PLLCLKEN	PLLEN
R-0-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 3-44 SYSPLLCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-5	RESERVED	R-0	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	PLLCLKEN	R/W	0h	SYSPLL bypassed or included in the PLLSYSCLK path: This bit decides if the SYSPLL is bypassed when PLLSYSCLK is generated 1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the system. 0 = SYSPLL is bypassed. Clock to system is direct feed from OSCCLK Note: Any writes to this bit must be followed with at least 120 CPU Cycles of wait time by adding at least 120 NOP instructions. Reset type: XRSn
0	PLLEN	R/W	0h	SYSPLL enabled or disabled: This bit decides if the SYSPLL is enabled or not 1 = SYSPLL is enabled 0 = SYSPLL is powered off. Clock to system is direct feed from OSCCLK Note: Any writes to this bit must be followed with at least 60 CPU Cycles of wait time by adding at least 60 NOP instructions. Reset type: XRSn

3.16.3.7 SYSPLLMULT Register (Offset = 14h) [Reset = 00000000h]

SYSPLLMULT is shown in Figure 3-45 and described in Table 3-45.

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SYSPLL Multiplier register

NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and cause system hangup.

This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-45 SYSPLLMULT Register

31	30	29	28	27	26	25	24
RESERVED			REFDIV
R-0-0h			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			ODIV
R-0-0h			R/W-0h

15	14	13	12	11	10	9	8
RESERVED		RESERVED		RESERVED		RESERVED
R-0-0h		R/W-0h		R-0-0h		R/W-0h

7	6	5	4	3	2	1	0
IMULT
R/W-0h

Table 3-45 SYSPLLMULT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R-0	0h	Reserved
28-24	REFDIV	R/W	0h	SYSPLL Reference Clock Divider PLL Reference Divider = REFDIV + 1 NOTE: IMULT and REFDIV fields in this register must be written at the same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and cause system hangup. Reset type: XRSn
23-21	RESERVED	R-0	0h	Reserved
20-16	ODIV	R/W	0h	SYSPLL Output Clock Divider PLL Output Divider = ODIV + 1 ODIV should be set to at least 1 to ensure the PLL output meets system duty cycle requirements. NOTE: If PLL is powered when SYSPLLCTL1.PLLCLKEN=0, then it is recommended to write IMULT, REFDIV and ODIV at the same time. This field can ALSO be programmed after SYSPLLCTL1.PLLCLKEN=1 if application desires to change the output divider of PLL clock, but proper care must be taken to make sure values of IMULT and REFDIV are left unchanged when SYSPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are change after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and cause system hangup. Reset type: XRSn
15-14	RESERVED	R-0	0h	Reserved
13-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R-0	0h	Reserved
9-8	RESERVED	R/W	0h	Reserved
7-0	IMULT	R/W	0h	SYSPLL Integer Multiplier: For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1 0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ....... 1111111 Integer Multipler = 127 NOTE: IMULT and REFDIV fields in this register must be written at the same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL opeartion and cause system hangup. Reset type: XRSn

3.16.3.8 SYSPLLSTS Register (Offset = 16h) [Reset = 00000000h]

SYSPLLSTS is shown in Figure 3-46 and described in Table 3-46.

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SYSPLL Status register

Figure 3-46 SYSPLLSTS Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	RESERVED	SLIPS_NOTSUPPORTED	LOCKS
R-0-0h				R-0h	R-0h	R-0h	R-0h

Table 3-46 SYSPLLSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-4	RESERVED	R-0	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	SLIPS_NOTSUPPORTED	R	0h	RESERVED: This bit is reserved and the value read should be ignored. TI recommends using DCC to evaluate SYSPLL Slip status. Refer to InitSysPll() or SysCtl_setClock() functions inside the latest example software from C2000Ware for checking SYSPLL Slip status using DCC. Reset type: XRSn
0	LOCKS	R	0h	SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is locked or not 0 = SYSPLL is not yet locked 1 = SYSPLL is locked Reset type: XRSn

3.16.3.9 AUXPLLCTL1 Register (Offset = 18h) [Reset = 00000000h]

AUXPLLCTL1 is shown in Figure 3-47 and described in Table 3-47.

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AUXPLL Control register-1

Figure 3-47 AUXPLLCTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	RESERVED	RESERVED	PLLCLKEN	PLLEN
R-0-0h			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 3-47 AUXPLLCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-5	RESERVED	R-0	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	PLLCLKEN	R/W	0h	AUXPLL bypassed or included in the AUXPLLCLK path: This bit decides if the AUXPLL is bypassed when AUXPLLCLK is generated 1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the AUXPLLCLK connected modules. 0 = AUXPLL is bypassed. Clock to modules connected to AUXPLLCLK is direct feed from AUXOSCCLK Reset type: XRSn
0	PLLEN	R/W	0h	AUXPLL enabled or disabled: This bit decides if the AUXPLL is enabled or not 1 = AUXPLL is enabled 0 = AUXPLL is powered off. Clock to system is direct feed from AUXOSCCLK Reset type: XRSn

3.16.3.10 AUXPLLMULT Register (Offset = 1Eh) [Reset = 00000000h]

AUXPLLMULT is shown in Figure 3-48 and described in Table 3-48.

Return to the Summary Table.

AUXPLL Multiplier register

NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-48 AUXPLLMULT Register

31	30	29	28	27	26	25	24
RESERVED			REFDIV
R-0-0h			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			ODIV
R-0-0h			R/W-0h

15	14	13	12	11	10	9	8
RESERVED		RESERVED		RESERVED		RESERVED
R-0-0h		R/W-0h		R-0-0h		R/W-0h

7	6	5	4	3	2	1	0
IMULT
R/W-0h

Table 3-48 AUXPLLMULT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R-0	0h	Reserved
28-24	REFDIV	R/W	0h	AUXPLL Reference Clock Divider PLL Reference Divider = REFDIV + 1 NOTE: IMULT and REFDIV fields in this register must be written at the same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation. Reset type: XRSn
23-21	RESERVED	R-0	0h	Reserved
20-16	ODIV	R/W	0h	AUXPLL Output Clock Divider PLL Output Divider = ODIV + 1 ODIV should be set to at least 1 to ensure the PLL output meets system duty cycle requirements. NOTE: If PLL is powered when AUXPLLCTL1.PLLCLKEN=0, then it is recommended to write IMULT, REFDIV and ODIV at the same time. This field can ALSO be programmed after AUXPLLCTL1.PLLCLKEN=1 if application desires to change the output divider of PLL clock, but proper care must be taken to make sure values of IMULT and REFDIV are left unchanged when AUXPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are change after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation. Reset type: XRSn
15-14	RESERVED	R-0	0h	Reserved
13-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R-0	0h	Reserved
9-8	RESERVED	R/W	0h	Reserved
7-0	IMULT	R/W	0h	AUXPLL Integer Multiplier: For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1 0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ....... 1111111 Integer Multipler = 127 NOTE: IMULT and REFDIV fields in this register must be written at the same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation. Reset type: XRSn

3.16.3.11 AUXPLLSTS Register (Offset = 20h) [Reset = 00000000h]

AUXPLLSTS is shown in Figure 3-49 and described in Table 3-49.

Return to the Summary Table.

AUXPLL Status register

Figure 3-49 AUXPLLSTS Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	RESERVED	SLIPS_NOTSUPPORTED	LOCKS
R-0-0h				R-0h	R-0h	R-0h	R-0h

Table 3-49 AUXPLLSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-4	RESERVED	R-0	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	SLIPS_NOTSUPPORTED	R	0h	RESERVED: This bit is reserved and the value read should be ignored. TI recommends using DCC to evaluate AUXPLL Slip status. Refer to InitAuxPll() or SysCtl_setAuxClock() functions inside the latest example software from C2000Ware for checking AUXPLL Slip status using DCC. Reset type: XRSn
0	LOCKS	R	0h	AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is locked or not 0 = AUXPLL is not yet locked 1 = AUXPLL is locked Reset type: XRSn

3.16.3.12 SYSCLKDIVSEL Register (Offset = 22h) [Reset = 00000000h]

SYSCLKDIVSEL is shown in Figure 3-50 and described in Table 3-50.

Return to the Summary Table.

System Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-50 SYSCLKDIVSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										PLLSYSCLKDIV
R-0-0h										R/W-0h

Table 3-50 SYSCLKDIVSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-6	RESERVED	R-0	0h	Reserved
5-0	PLLSYSCLKDIV	R/W	0h	PLLSYSCLK Divide Select: This bit selects the divider setting for the PLLSYSCLK. 0000 = /1 0001 = /2 0010 = /4 0011 = /6 0100 = /8 0101 = /10 0110 = /12 0111 = /14 1000 = /16 Others: Reserved Reset type: XRSn

3.16.3.13 AUXCLKDIVSEL Register (Offset = 24h) [Reset = 00001301h]

AUXCLKDIVSEL is shown in Figure 3-51 and described in Table 3-51.

Return to the Summary Table.

Auxillary Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-51 AUXCLKDIVSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			MCANCLKDIV					RESERVED					AUXPLLDIV
R-0-0h			R/W-13h					R-0-0h					R/W-1h

Table 3-51 AUXCLKDIVSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R-0	0h	Reserved
12-8	MCANCLKDIV	R/W	13h	This bit-field divides the source clock (chosen by the CLKSRCCTL2.MCANABITCLKSEL bit-field) before feeding it as the bit-clock to the MCAN module 00000 = /1 00001 = /2 ... 10010 = /19 10011 = /20 101xx = Rsvd 11xxx = Rsvd Reset type: XRSn
7-3	RESERVED	R-0	0h	Reserved
2-0	AUXPLLDIV	R/W	1h	AUXPLLCLK Divide Select: This bit selects the divider setting for the AUXPLLCK. 000 = /1 001 = /2 (default on reset) 010 = /4 011 = /8 100 = /3 101 = /5 110 = /6 111 = /7 Reset type: XRSn

3.16.3.14 PERCLKDIVSEL Register (Offset = 26h) [Reset = 00000051h]

PERCLKDIVSEL is shown in Figure 3-52 and described in Table 3-52.

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Peripheral Clock Divider Selet register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-52 PERCLKDIVSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED	EMIF2CLKDIV	RESERVED	EMIF1CLKDIV	RESERVED		EPWMCLKDIV
R-0-0h	R/W-1h	R-0-0h	R/W-1h	R/W-0h		R/W-1h

Table 3-52 PERCLKDIVSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-7	RESERVED	R-0	0h	Reserved
6	EMIF2CLKDIV	R/W	1h	EMIF2 Clock Divide Select: This bit selects whether the EMIF2 module run with a /1 or /2 clock. 0: /1 of CPU1.SYSCLK is selected 1: /2 of CPU1.SYSCLK is selected Reset type: CPU1.SYSRSn
5	RESERVED	R-0	0h	Reserved
4	EMIF1CLKDIV	R/W	1h	EMIF1 Clock Divide Select: This bit selects whether the EMIF1 module run with a /1 or /2 clock. For single core device 0: /1 of CPU1.SYSCLK is selected 1: /2 of CPU1.SYSCLK is selected For Dual core device 0: /1 of PLLSYSCLK is selected 1: /2 of PLLSYSCLK is selected Reset type: CPU1.SYSRSn
3-2	RESERVED	R/W	0h	Reserved
1-0	EPWMCLKDIV	R/W	1h	EPWM Clock Divide Select: This bit selects whether the EPWM modules run with a /1 or /2 clock. This divider sits in front of the PLLSYSCLK x0 = /1 of PLLSYSCLK x1 = /2 of PLLSYSLCK (default on reset) Note: Refer to the EPWM User Guide for maximum EPWM Frequency Reset type: CPU1.SYSRSn

3.16.3.15 XCLKOUTDIVSEL Register (Offset = 28h) [Reset = 00000003h]

XCLKOUTDIVSEL is shown in Figure 3-53 and described in Table 3-53.

Return to the Summary Table.

XCLKOUT Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-53 XCLKOUTDIVSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED						XCLKOUTDIV
R-0-0h						R/W-3h

Table 3-53 XCLKOUTDIVSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-2	RESERVED	R-0	0h	Reserved
1-0	XCLKOUTDIV	R/W	3h	XCLKOUT Divide Select: This bit selects the divider setting for the XCLKOUT. 00 = /1 01 = /2 10 = /4 11 = /8 (default on reset) Reset type: CPU1.SYSRSn

3.16.3.16 CLBCLKCTL Register (Offset = 2Ah) [Reset = 00000007h]

CLBCLKCTL is shown in Figure 3-54 and described in Table 3-54.

Return to the Summary Table.

CLB Clocking Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-54 CLBCLKCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
CLKMODECLB8	CLKMODECLB7	CLKMODECLB6	CLKMODECLB5	CLKMODECLB4	CLKMODECLB3	CLKMODECLB2	CLKMODECLB1
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED			TILECLKDIV	RESERVED	CLBCLKDIV
R-0-0h			R/W-0h	R-0-0h	R/W-7h

Table 3-54 CLBCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R-0	0h	Reserved
23	CLKMODECLB8	R/W	0h	0 : CLB8 is synchronous to SYSCLK 1 : CLB8 runs of asynchronous clock Reset type: SYSRSn
22	CLKMODECLB7	R/W	0h	0 : CLB7 is synchronous to SYSCLK 1 : CLB7 runs of asynchronous clock Reset type: SYSRSn
21	CLKMODECLB6	R/W	0h	0 : CLB6 is synchronous to SYSCLK 1 : CLB6 runs of asynchronous clock Reset type: SYSRSn
20	CLKMODECLB5	R/W	0h	0 : CLB5 is synchronous to SYSCLK 1 : CLB5 runs of asynchronous clock Reset type: SYSRSn
19	CLKMODECLB4	R/W	0h	0 : CLB4 is synchronous to SYSCLK 1 : CLB4 runs of asynchronous clock Reset type: SYSRSn
18	CLKMODECLB3	R/W	0h	0 : CLB3 is synchronous to SYSCLK 1 : CLB3 runs of asynchronous clock Reset type: SYSRSn
17	CLKMODECLB2	R/W	0h	0 : CLB2 is synchronous to SYSCLK 1 : CLB2 runs of asynchronous clock Reset type: SYSRSn
16	CLKMODECLB1	R/W	0h	0 : CLB1 is synchronous to SYSCLK 1 : CLB1 runs of asynchronous clock Reset type: SYSRSn
15-5	RESERVED	R-0	0h	Reserved
4	TILECLKDIV	R/W	0h	0: /1 1: /2 Reset type: SYSRSn
3	RESERVED	R-0	0h	Reserved
2-0	CLBCLKDIV	R/W	7h	000: /1 001: /2 010: /3 011: /4 100: /5 101: /6 110: /7 111: /8 Reset type: SYSRSn

3.16.3.17 LOSPCP Register (Offset = 2Ch) [Reset = 00000002h]

LOSPCP is shown in Figure 3-55 and described in Table 3-55.

Return to the Summary Table.

Low Speed Clock Source Prescalar

Figure 3-55 LOSPCP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													LSPCLKDIV
R-0-0h													R/W-2h

Table 3-55 LOSPCP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-3	RESERVED	R-0	0h	Reserved
2-0	LSPCLKDIV	R/W	2h	These bits configure the low-speed peripheral clock (LSPCLK) rate relative to SYSCLK of CPU1 and CPU2. 000,LSPCLK = / 1 001,LSPCLK = / 2 010,LSPCLK = / 4 (default on reset) 011,LSPCLK = / 6 100,LSPCLK = / 8 101,LSPCLK = / 10 110,LSPCLK = / 12 111,LSPCLK = / 14 Note: [1] This clock is used as strobe for the SCI and SPI modules. Reset type: CPU1.SYSRSn

3.16.3.18 MCDCR Register (Offset = 2Eh) [Reset = 00000000h]

MCDCR is shown in Figure 3-56 and described in Table 3-56.

Return to the Summary Table.

Missing Clock Detect Control Register

Figure 3-56 MCDCR Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED				OSCOFF	MCLKOFF	MCLKCLR	MCLKSTS
R-0-0h				R/W-0h	R/W-0h	R-0/W1S-0h	R-0h

Table 3-56 MCDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R-0	0h	Reserved
15-4	RESERVED	R-0	0h	Reserved
3	OSCOFF	R/W	0h	Oscillator Clock Disconnect from MCD Bit: 0 = OSCCLK Connected to OSCCLK Counter in MCD module 1 = OSCCLK Disconnected to OSCCLK Counter in MCD module Reset type: XRSn
2	MCLKOFF	R/W	0h	Missing Clock Detect Off Bit: 0 = Missing Clock Detect Circuit Enabled 1 = Missing Clock Detect Circuit Disabled Reset type: XRSn
1	MCLKCLR	R-0/W1S	0h	Missing Clock Clear Bit: Write 1' to this bit to clear MCLKSTS bit and reset the missing clock detect circuit.' Reset type: XRSn
0	MCLKSTS	R	0h	Missing Clock Status Bit: 0 = OSCCLK Is OK 1 = OSCCLK Detected Missing, CLOCKFAILn Generated Reset type: XRSn

3.16.3.19 X1CNT Register (Offset = 30h) [Reset = 00000000h]

X1CNT is shown in Figure 3-57 and described in Table 3-57.

Return to the Summary Table.

10-bit Counter on X1 Clock

Figure 3-57 X1CNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED															CLR
R-0-0h															R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						X1CNT
R-0-0h						R-0h

Table 3-57 X1CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R-0	0h	Reserved
16	CLR	R/W	0h	X1 Counter clear: 1: X1CNT clear is asserted 0: X1CNT clear is de-asserted Reset type: XRSn
15-10	RESERVED	R-0	0h	Reserved
9-0	X1CNT	R	0h	X1 Counter: - This counter increments on every X1 CLOCKs positive-edge. - Once it reaches the values of 0x3ff, it freezes - Before switching from INTOSC2 to X1, application must check this counter and make sure that it has saturated. This will ensure that the Crystal connected to X1/X2 is oscillating. Note: Before switching the OSCCCLKSRC to X1, X1CNT register needs to be read at least 3 times for 0x3FF value. Refer C2000Ware function 'SysCtl_pollX1Counter' for SW implementation. Reset type: XRSn

3.16.3.20 XTALCR Register (Offset = 32h) [Reset = 00000004h]

XTALCR is shown in Figure 3-58 and described in Table 3-58.

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XTAL Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-58 XTALCR Register

31	30	29	28	27	26	25	24
RESERVED
R-0-0h

23	22	21	20	19	18	17	16
RESERVED
R-0-0h

15	14	13	12	11	10	9	8
RESERVED
R-0-0h

7	6	5	4	3	2	1	0
RESERVED					RESERVED	SE	OSCOFF
R-0-0h					R/W-1h	R/W-0h	R/W-0h

Table 3-58 XTALCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R-0	0h	Reserved
2	RESERVED	R/W	1h	Reserved
1	SE	R/W	0h	Configures XTAL oscillator in single-ended or Crystal mode when XTAL oscillator is powered (OFF = 0) 0 XTAL oscillator in Crystal mode 1 XTAL oscilator in single0ended mode (through X1) Reset type: XRSn
0	OSCOFF	R/W	0h	This bit if '1', powers-down the XTAL oscillator macro and hence doesn't let X2 to be driven by the XTAL oscillator. If a crystal is connected to X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2 Reset type: XRSn

3.16.3.21 ETHERCATCLKCTL Register (Offset = 36h) [Reset = 0000000Eh]

ETHERCATCLKCTL is shown in Figure 3-59 and described in Table 3-59.

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ETHERCAT clock control register.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-59 ETHERCATCLKCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							PHYCLKEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				ECATDIV			DIVSRCSEL
R-0-0h				R/W-7h			R/W-0h

Table 3-59 ETHERCATCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	PHYCLKEN	R/W	0h	0 : etherCAT phy clock disabled 1 : etherCAT phy clock enabled Reset type: XRSn
7-4	RESERVED	R-0	0h	Reserved
3-1	ECATDIV	R/W	7h	000: /1 001: /2 010: /3 011: /4 100: /5 101: /6 110: /7 111: /8 Reset type: XRSn
0	DIVSRCSEL	R/W	0h	0: Auxillary PLL is the source for the etherCAT clock divider. 1: System PLL is the source for etherCAT clock divider. Reset type: XRSn

3.16.3.22 CMCLKCTL Register (Offset = 38h) [Reset = 000000E6h]

CMCLKCTL is shown in Figure 3-60 and described in Table 3-60.

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CM Clock control register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-60 CMCLKCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
ETHDIV			ETHDIVSRCSEL	CMCLKDIV			CMDIVSRCSEL
R/W-7h			R/W-0h	R/W-3h			R/W-0h

Table 3-60 CMCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-5	ETHDIV	R/W	7h	000: /1 001: /2 010: /3 011: /4 100: /5 101: /6 110: /7 111: /8 Reset type: XRSn
4	ETHDIVSRCSEL	R/W	0h	0: Auxillary PLL is the source for the etherNET clock divider. 1: System PLL is the source for etherNET clock divider. Reset type: XRSn
3-1	CMCLKDIV	R/W	3h	000: /1 001: /2 010: /3 011: /4 100: /5 101: /6 110: /7 111: /8 Note: CMCLKDIV should be configured prior or along with CMCLKDIV configuration. If CMCLKDIV is configured after CMDIVSRCSEL in the next cycle, the writes to this field gets ignored. Reset type: XRSn
0	CMDIVSRCSEL	R/W	0h	0: Auxillary PLL is the source for the CM clock divider. 1: System PLL is the source for CM clock divider. Reset type: XRSn