SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

12.2.5.2 Interfacing to SDRAM

The EMIF supports a glueless interface to SDRAM devices with the following characteristics:

Pre-charge bit is A[10]
The number of column address bits is 8, 9, 10, or 11.
The number of row address bits is 13, 14, 15, or 16.
The number of internal banks is 1, 2, or 4.

Figure 12-4 shows an interface between the EMIF and a 2M × 16 × 4 bank SDRAM device, and Figure 12-5 shows an interface between the EMIF and a 512K × 16 × 2 bank SDRAM device. For devices supporting 16-bit interface, refer to Table 12-7 for list of commonly-supported SDRAM devices and the required connections for the address pins.

F2838x EMIF to 2M × 16 × 4 Bank SDRAM
Interface

Figure 12-4 EMIF to 2M × 16 × 4 Bank SDRAM Interface

F2838x EMIF to 512K × 16 × 2 Bank
SDRAM Interface

Figure 12-5 EMIF to 512K × 16 × 2 Bank SDRAM Interface

Table 12-7 16-bit EMIF Address Pin Connections

SDRAM Size	Width	Banks	Device	Address Pins
16M bits	×16	2	SDRAM	A[10:0]
16M bits	×16	2	EMIF	EM1A[10:0]
64M bits	×16	4	SDRAM	A[11:0]
64M bits	×16	4	EMIF	EM1A[11:0]
128M bits	×16	4	SDRAM	A[11:0]
128M bits	×16	4	EMIF	EM1A[11:0]
256M bits	x16	4	SDRAM	A[12:0]
256M bits	x16	4	EMIF	EM1A[12:0]
512M bits	x16	4	SDRAM	A[12:0]
512M bits	x16	4	EMIF	EM1A[12:0]