SPRUII0F May   2019  â€“ June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C28x SYSTEM RESOURCES
    1. 1.1 Technical Reference Manual Overview
  4. 2 C2000â„¢ Microcontrollers Software Support
    1. 2.1 Introduction
    2. 2.2 C2000Ware Structure
    3. 2.3 Documentation
    4. 2.4 Devices
    5. 2.5 Libraries
    6. 2.6 Code Composer Studioâ„¢ Integrated Development Environment (IDE)
    7. 2.7 SysConfig and PinMUX Tool
  5. 3 C28x System Control and Interrupts
    1. 3.1  C28x System Control Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRSn)
      3. 3.3.3  Simulate External Reset
      4. 3.3.4  Power-On Reset (POR)
      5. 3.3.5  Debugger Reset (SYSRS)
      6. 3.3.6  Simulate CPU1 Reset
      7. 3.3.7  Watchdog Reset (WDRS)
      8. 3.3.8  NMI Watchdog Reset (NMIWDRS)
      9. 3.3.9  Secure Code Copy Reset (SCCRESET)
      10. 3.3.10 ESC Reset Output
      11. 3.3.11 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 System Error and CM Status Interrupts
      7. 3.4.7 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1  Missing Clock Detection
        2. 3.5.3.2  RAM Uncorrectable Error
        3. 3.5.3.3  Flash Uncorrectable ECC Error
        4. 3.5.3.4  ROM Uncorrectable Error
        5. 3.5.3.5  NMI Vector Fetch Mismatch
        6. 3.5.3.6  CPU2 Watchdog or NMI Watchdog Reset
        7. 3.5.3.7  CM NMI Watchdog Reset
        8. 3.5.3.8  EtherCAT Reset out
        9. 3.5.3.9  CRC Fail
        10. 3.5.3.10 ERAD NMI
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check
      3. 3.6.3 NMIWDs
      4. 3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
      5. 3.6.5 ECC Enabled Flash Memory
      6. 3.6.6 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 External Clock Output (XCLKOUT)
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 PLL/AUXPLL
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 SYS PLL / AUX PLL Bypass
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  Clock Configuration Semaphore
    9. 3.9  32-Bit CPU Timers 0/1/2
    10. 3.10 Watchdog Timers
      1. 3.10.1 Servicing the Watchdog Timer
      2. 3.10.2 Minimum Window Check
      3. 3.10.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.10.4 Watchdog Operation in Low-Power Modes
      5. 3.10.5 Emulation Considerations
    11. 3.11 Low-Power Modes
      1. 3.11.1 IDLE
      2. 3.11.2 STANDBY
    12. 3.12 Memory Controller Module
      1. 3.12.1 Functional Description
        1. 3.12.1.1  Dedicated RAM (Dx RAM)
        2. 3.12.1.2  Local Shared RAM (LSx RAM)
        3. 3.12.1.3  Global Shared RAM (GSx RAM)
        4. 3.12.1.4  CPU Message RAM (CPU MSG RAM)
        5. 3.12.1.5  CLA Message RAM (CLA MSGRAM)
        6. 3.12.1.6  CLA-DMA MSG RAM
        7. 3.12.1.7  Access Arbitration
        8. 3.12.1.8  Access Protection
          1. 3.12.1.8.1 CPU Fetch Protection
          2. 3.12.1.8.2 CPU Write Protection
          3. 3.12.1.8.3 CPU Read Protection
          4. 3.12.1.8.4 CLA Fetch Protection
          5. 3.12.1.8.5 CLA Write Protection
          6. 3.12.1.8.6 CLA Read Protection
          7. 3.12.1.8.7 DMA Write Protection
        9. 3.12.1.9  Memory Error Detection, Correction and Error Handling
          1. 3.12.1.9.1 Error Detection and Correction
          2. 3.12.1.9.2 Error Handling
        10. 3.12.1.10 Application Test Hooks for Error Detection and Correction
        11. 3.12.1.11 ROM Test
        12. 3.12.1.12 RAM Initialization
    13. 3.13 JTAG
      1. 3.13.1 JTAG Noise and TAP_STATUS
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1 SYSCTL Examples
        1. 3.15.1.1 Missing clock detection (MCD)
        2. 3.15.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.15.2 MEMCFG Examples
        1. 3.15.2.1 Correctable & Uncorrectable Memory Error Handling
        2. 3.15.2.2 Shared RAM Management (CPU1) - C28X_DUAL
        3. 3.15.2.3 Shared RAM Management (CPU2) - C28X_DUAL
        4. 3.15.2.4 Demonstrate memconfig diagnostics and error handling. - CM
        5. 3.15.2.5 Shared RAM Management (CPU1) - C28X_DUAL
        6. 3.15.2.6 Shared RAM Management (CPU2) - C28X_DUAL
      3. 3.15.3 NMI Examples
        1. 3.15.3.1 NMI handling - C28X_DUAL
        2. 3.15.3.2 Watchdog Reset - C28X_DUAL
        3. 3.15.3.3 NMI handling - C28X_DUAL
        4. 3.15.3.4 Watchdog Reset - C28X_DUAL
      4. 3.15.4 TIMER Examples
        1. 3.15.4.1 CPU Timers
        2. 3.15.4.2 CPU Timers - CM
        3. 3.15.4.3 CPU Timers
      5. 3.15.5 WATCHDOG Examples
        1. 3.15.5.1 Watchdog
        2. 3.15.5.2 Windowed watchdog expiry with NMI handling - CM
    16. 3.16 System Control Registers
      1. 3.16.1  SYSCTRL Base Address Table (C28)
      2. 3.16.2  ACCESS_PROTECTION_REGS Registers
      3. 3.16.3  CLK_CFG_REGS Registers
      4. 3.16.4  CM_CONF_REGS Registers
      5. 3.16.5  CPU_SYS_REGS Registers
      6. 3.16.6  CPU_ID_REGS Registers
      7. 3.16.7  CPU1_PERIPH_AC_REGS Registers
      8. 3.16.8  CPUTIMER_REGS Registers
      9. 3.16.9  DEV_CFG_REGS Registers
      10. 3.16.10 DMA_CLA_SRC_SEL_REGS Registers
      11. 3.16.11 MEM_CFG_REGS Registers
      12. 3.16.12 MEMORY_ERROR_REGS Registers
      13. 3.16.13 NMI_INTRUPT_REGS Registers
      14. 3.16.14 PIE_CTRL_REGS Registers
      15. 3.16.15 ROM_PREFETCH_REGS Registers
      16. 3.16.16 ROM_WAIT_STATE_REGS Registers
      17. 3.16.17 SYNC_SOC_REGS Registers
      18. 3.16.18 SYS_STATUS_REGS Registers
      19. 3.16.19 TEST_ERROR_REGS Registers
      20. 3.16.20 UID_REGS Registers
      21. 3.16.21 WD_REGS Registers
      22. 3.16.22 XINT_REGS Registers
      23. 3.16.23 Register to Driverlib Function Mapping
        1. 3.16.23.1 ASYSCTL Registers to Driverlib Functions
        2. 3.16.23.2 CPUTIMER Registers to Driverlib Functions
        3. 3.16.23.3 DCSM Registers to Driverlib Functions
        4. 3.16.23.4 MEMCFG Registers to Driverlib Functions
        5. 3.16.23.5 NMI Registers to Driverlib Functions
        6. 3.16.23.6 PIE Registers to Driverlib Functions
        7. 3.16.23.7 SYSCTL Registers to Driverlib Functions
        8. 3.16.23.8 WWD Registers to Driverlib Functions
        9. 3.16.23.9 XINT Registers to Driverlib Functions
  6. 4 C28x Processor
    1. 4.1 Introduction
    2. 4.2 C28X Related Collateral
    3. 4.3 Features
    4. 4.4 Floating-Point Unit
    5. 4.5 Trigonometric Math Unit (TMU)
    6. 4.6 VCRC Unit
  7. 5 ROM Code and Peripheral Booting
    1. 5.1 Introduction
      1. 5.1.1 ROM Related Collateral
    2. 5.2 Device Boot Sequence
    3. 5.3 Device Boot Modes
    4. 5.4 Device Boot Configurations
      1. 5.4.1 Configuring Boot Mode Pins for CPU1
      2. 5.4.2 Configuring Boot Mode Table Options for CPU1
      3. 5.4.3 Boot Mode Example Use Cases
        1. 5.4.3.1 Zero Boot Mode Select Pins
        2. 5.4.3.2 One Boot Mode Select Pin
        3. 5.4.3.3 Three Boot Mode Select Pins
    5. 5.5 Device Boot Flow Diagrams
      1. 5.5.1 CPU1 Boot Flow
      2. 5.5.2 CPU2 Boot Flow
      3. 5.5.3 Connectivity Manager (CM) Boot Flow
    6. 5.6 Device Reset and Exception Handling
      1. 5.6.1 Reset Causes and Handling
      2. 5.6.2 Exceptions and Interrupts Handling
    7. 5.7 Boot ROM Description
      1. 5.7.1  CPU1 Boot ROM Configuration Registers
        1. 5.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 5.7.2  Booting CPU2 and CM
        1. 5.7.2.1 Boot Up Procedure
        2. 5.7.2.2 IPCBOOTMODE Details
        3. 5.7.2.3 Error IPC Command Table
      3. 5.7.3  Entry Points
      4. 5.7.4  Wait Points
      5. 5.7.5  Memory Maps
        1. 5.7.5.1 Boot ROM Memory Maps
        2. 5.7.5.2 CLA Data ROM Memory Maps
        3. 5.7.5.3 Reserved RAM Memory Maps
      6. 5.7.6  ROM Tables
      7. 5.7.7  Boot Modes and Loaders
        1. 5.7.7.1 Boot Modes
          1. 5.7.7.1.1 Wait Boot
          2. 5.7.7.1.2 Flash Boot
          3. 5.7.7.1.3 Secure Flash Boot
            1. 5.7.7.1.3.1 Secure Flash CPU1 Linker File Example
          4. 5.7.7.1.4 RAM Boot
          5. 5.7.7.1.5 User OTP Boot
          6. 5.7.7.1.6 IPC Message Copy to RAM Boot
        2. 5.7.7.2 Bootloaders
          1. 5.7.7.2.1 SCI Boot Mode
          2. 5.7.7.2.2 SPI Boot Mode
          3. 5.7.7.2.3 I2C Boot Mode
          4. 5.7.7.2.4 Parallel Boot Mode
          5. 5.7.7.2.5 CAN Boot Mode
          6. 5.7.7.2.6 USB Boot Mode
      8. 5.7.8  GPIO Assignments for CPU1
      9. 5.7.9  Secure ROM Function APIs
      10. 5.7.10 Clock Initializations
      11. 5.7.11 Boot Status information
        1. 5.7.11.1 CPU1 Booting Status
        2. 5.7.11.2 CPU2 Booting Status
        3. 5.7.11.3 CM Booting Status
        4. 5.7.11.4 Boot Mode and MPOST (Memory Power On Self-Test) Status
      12. 5.7.12 ROM Version
    8. 5.8 Application Notes for Using the Bootloaders
      1. 5.8.1 Boot Data Stream Structure
        1. 5.8.1.1 Bootloader Data Stream Structure
          1. 5.8.1.1.1 Data Stream Structure 8-bit
      2. 5.8.2 The C2000 Hex Utility
        1. 5.8.2.1 HEX2000.exe Command Syntax
    9. 5.9 Software
      1. 5.9.1 BOOT Examples
        1. 5.9.1.1 CM Secure Flash Boot
        2. 5.9.1.2 CPU1 Secure Flash Boot
        3. 5.9.1.3 CPU2 Secure Flash Boot
  8. 6 Dual Code Security Module (DCSM)
    1. 6.1 Introduction
      1. 6.1.1 DCSM Related Collateral
    2. 6.2 Functional Description
      1. 6.2.1 CSM Passwords
      2. 6.2.2 Emulation Code Security Logic (ECSL)
      3. 6.2.3 CPU Secure Logic
      4. 6.2.4 Execute-Only Protection
      5. 6.2.5 Password Lock
      6. 6.2.6 JTAGLOCK
      7. 6.2.7 Link Pointer and Zone Select
      8. 6.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 6.3 Flash and OTP Erase/Program
    4. 6.4 Secure Copy Code
    5. 6.5 SecureCRC
    6. 6.6 CSM Impact on Other On-Chip Resources
    7. 6.7 Incorporating Code Security in User Applications
      1. 6.7.1 Environments That Require Security Unlocking
      2. 6.7.2 CSM Password Match Flow
      3. 6.7.3 C Code Example to Unsecure C28x Zone1
      4. 6.7.4 C Code Example to Resecure C28x Zone1
      5. 6.7.5 Environments That Require ECSL Unlocking
      6. 6.7.6 ECSL Password Match Flow
      7. 6.7.7 ECSL Disable Considerations for any Zone
        1. 6.7.7.1 C Code Example to Disable ECSL for C28x-Zone1
      8. 6.7.8 Device Unique ID
    8. 6.8 Software
      1. 6.8.1 DCSM Examples
        1. 6.8.1.1 Empty DCSM Tool Example
        2. 6.8.1.2 DCSM Memory Access control by master CPU1 - C28X_CM
        3. 6.8.1.3 DCSM Memory Access by CPU2 - C28X_DUAL
        4. 6.8.1.4 DCSM Memory Access control by CPU1 - C28X_DUAL
        5. 6.8.1.5 DCSM Memory partitioning Example
        6. 6.8.1.6 DCSM Memory Access by CM - C28X_CM
    9. 6.9 DCSM Registers
      1. 6.9.1 DCSM Base Address Table (C28)
      2. 6.9.2 CM DCSM Base Address Table (CM)
      3. 6.9.3 DCSM_Z1_REGS Registers
      4. 6.9.4 DCSM_Z2_REGS Registers
      5. 6.9.5 DCSM_COMMON_REGS Registers
      6. 6.9.6 DCSM_Z1_OTP Registers
      7. 6.9.7 DCSM_Z2_OTP Registers
  9. 7 Background CRC-32 (BGCRC)
    1. 7.1 Introduction
      1. 7.1.1 BGCRC Related Collateral
      2. 7.1.2 Features
      3. 7.1.3 Block Diagram
      4. 7.1.4 Memory Wait States and Memory Map
    2. 7.2 Functional Description
      1. 7.2.1 Data Read Unit
      2. 7.2.2 CRC-32 Compute Unit
      3. 7.2.3 CRC Notification Unit
        1. 7.2.3.1 CPU Interrupt, CLA Task and NMI
      4. 7.2.4 Operating Modes
        1. 7.2.4.1 CRC Mode
        2. 7.2.4.2 Scrub Mode
      5. 7.2.5 BGCRC Watchdog
      6. 7.2.6 Hardware and Software Faults Protection
    3. 7.3 Application of the BGCRC
      1. 7.3.1 Software Configuration
      2. 7.3.2 Decision on Error Response Severity
      3. 7.3.3 Decision of Controller for CLA_CRC
      4. 7.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 7.3.5 BGCRC Execution
      6. 7.3.6 Debug/Error Response for BGCRC Errors
      7. 7.3.7 BGCRC Golden CRC-32 Value Computation
    4. 7.4 Software
      1. 7.4.1 BGCRC Examples
        1. 7.4.1.1 BGCRC CPU Interrupt Example
        2. 7.4.1.2 BGCRC Example with Watchdog and Lock
        3. 7.4.1.3 CLA-BGCRC Example in CRC mode
        4. 7.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 7.5 BGCRC Registers
      1. 7.5.1 BGCRC Base Address Table (C28)
      2. 7.5.2 BGCRC_REGS Registers
      3. 7.5.3 BGCRC Registers to Driverlib Functions
  10. 8 Control Law Accelerator (CLA)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 CLA Related Collateral
      3. 8.1.3 Block Diagram
    2. 8.2 CLA Interface
      1. 8.2.1 CLA Memory
      2. 8.2.2 CLA Memory Bus
      3. 8.2.3 Shared Peripherals and EALLOW Protection
      4. 8.2.4 CLA Tasks and Interrupt Vectors
      5. 8.2.5 CLA Software Interrupt to CPU
    3. 8.3 CLA, DMA, and CPU Arbitration
      1. 8.3.1 CLA Message RAM
      2. 8.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 8.4 CLA Configuration and Debug
      1. 8.4.1 Building a CLA Application
      2. 8.4.2 Typical CLA Initialization Sequence
      3. 8.4.3 Debugging CLA Code
        1. 8.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 8.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 8.4.4 CLA Illegal Opcode Behavior
      5. 8.4.5 Resetting the CLA
    5. 8.5 Pipeline
      1. 8.5.1 Pipeline Overview
      2. 8.5.2 CLA Pipeline Alignment
        1. 8.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       379
        3. 8.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       381
        5. 8.5.2.3 ADC Early Interrupt to CLA Response
      3. 8.5.3 Parallel Instructions
        1. 8.5.3.1 Math Operation with Parallel Load
        2. 8.5.3.2 Multiply with Parallel Add
      4. 8.5.4 CLA Task Execution Latency
    6. 8.6 Software
      1. 8.6.1 CLA Examples
        1. 8.6.1.1  CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 8.6.1.2  CLA arcsine(x) using a lookup table (cla_asin_cpu01) - C28X_DUAL
        3. 8.6.1.3  CLA Arcsine Example. - C28X_DUAL
        4. 8.6.1.4  CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        5. 8.6.1.5  CLA 2 Pole 2 Zero Infinite Impulse Response Filter (cla_iir2p2z_cpu01) - C28X_DUAL
        6. 8.6.1.6  CLA 2-pole 2-zero IIR Filter Example for F2837xD. - C28X_DUAL
        7. 8.6.1.7  CLA background nesting task
        8. 8.6.1.8  Controlling PWM output using CLA
        9. 8.6.1.9  Just-in-time ADC sampling with CLA
        10. 8.6.1.10 Optimal offloading of control algorithms to CLA
        11. 8.6.1.11 Handling shared resources across C28x and CLA
    7. 8.7 Instruction Set
      1. 8.7.1 Instruction Descriptions
      2. 8.7.2 Addressing Modes and Encoding
      3. 8.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 [, CNDF]
        47.       MMOV32 MRa, MRb [, CNDF]
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb[, CNDF]
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD [CNDF]
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb [, CNDF]
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 8.8 CLA Registers
      1. 8.8.1 CLA Base Address Table (C28)
      2. 8.8.2 CLA_ONLY_REGS Registers
      3. 8.8.3 CLA_SOFTINT_REGS Registers
      4. 8.8.4 CLA_REGS Registers
      5. 8.8.5 CLA Registers to Driverlib Functions
  11. 9 Configurable Logic Block (CLB)
    1. 9.1  Introduction
      1. 9.1.1 CLB Related Collateral
    2. 9.2  Description
      1. 9.2.1 CLB Clock
    3. 9.3  CLB Input/Output Connection
      1. 9.3.1 Overview
      2. 9.3.2 CLB Input Selection
      3. 9.3.3 CLB Output Selection
      4. 9.3.4 CLB Output Signal Multiplexer
    4. 9.4  CLB Tile
      1. 9.4.1 Static Switch Block
      2. 9.4.2 Counter Block
        1. 9.4.2.1 Counter Description
        2. 9.4.2.2 Counter Operation
        3. 9.4.2.3 Serializer Mode
        4. 9.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 9.4.3 FSM Block
      4. 9.4.4 LUT4 Block
      5. 9.4.5 Output LUT Block
      6. 9.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 9.4.7 High Level Controller (HLC)
        1. 9.4.7.1 High Level Controller Events
        2. 9.4.7.2 High Level Controller Instructions
        3. 9.4.7.3 <Src> and <Dest>
        4. 9.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 9.5  CPU Interface
      1. 9.5.1 Register Description
      2. 9.5.2 Non-Memory Mapped Registers
    6. 9.6  DMA Access
    7. 9.7  CLB Data Export Through SPI RX Buffer
    8. 9.8  CLB Pipeline Mode
    9. 9.9  Software
      1. 9.9.1 CLB Examples
        1. 9.9.1.1  CLB Empty Project
        2. 9.9.1.2  CLB Combinational Logic
        3. 9.9.1.3  CLB GPIO Input Filter
        4. 9.9.1.4  CLB Auxilary PWM
        5. 9.9.1.5  CLB PWM Protection
        6. 9.9.1.6  CLB Event Window
        7. 9.9.1.7  CLB Signal Generator
        8. 9.9.1.8  CLB State Machine
        9. 9.9.1.9  CLB External Signal AND Gate
        10. 9.9.1.10 CLB Timer
        11. 9.9.1.11 CLB Timer Two States
        12. 9.9.1.12 CLB Interrupt Tag
        13. 9.9.1.13 CLB Output Intersect
        14. 9.9.1.14 CLB PUSH PULL
        15. 9.9.1.15 CLB Multi Tile
        16. 9.9.1.16 CLB Tile to Tile Delay
        17. 9.9.1.17 CLB based One-shot PWM
        18. 9.9.1.18 CLB AOC Control
        19. 9.9.1.19 CLB AOC Release Control
        20. 9.9.1.20 CLB XBARs
        21. 9.9.1.21 CLB AOC Control
        22. 9.9.1.22 CLB Serializer
        23. 9.9.1.23 CLB LFSR
        24. 9.9.1.24 CLB Lock Output Mask
        25. 9.9.1.25 CLB INPUT Pipeline Mode
        26. 9.9.1.26 CLB Clocking and PIPELINE Mode
        27. 9.9.1.27 CLB SPI Data Export
        28. 9.9.1.28 CLB SPI Data Export DMA
        29. 9.9.1.29 CLB Trip Zone Timestamp
        30. 9.9.1.30 CLB CRC
    10. 9.10 CLB Registers
      1. 9.10.1 CLB Base Address Table (C28)
      2. 9.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 9.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 9.10.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 9.10.5 CLB Registers to Driverlib Functions
  12. 10Dual-Clock Comparator (DCC)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Module Operation
      1. 10.2.1 Configuring DCC Counters
      2. 10.2.2 Single-Shot Measurement Mode
      3. 10.2.3 Continuous Monitoring Mode
      4. 10.2.4 Error Conditions
    3. 10.3 Interrupts
    4. 10.4 Software
      1. 10.4.1 DCC Examples
        1. 10.4.1.1 DCC Single shot Clock verification
        2. 10.4.1.2 DCC Single shot Clock measurement
        3. 10.4.1.3 DCC Continuous clock monitoring
        4. 10.4.1.4 DCC Continuous clock monitoring
        5. 10.4.1.5 DCC Detection of clock failure
    5. 10.5 DCC Registers
      1. 10.5.1 DCC Base Address Table (C28)
      2. 10.5.2 DCC_REGS Registers
      3. 10.5.3 DCC Registers to Driverlib Functions
  13. 11Direct Memory Access (DMA)
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Architecture
      1. 11.2.1 Peripheral Interrupt Event Trigger Sources
      2. 11.2.2 DMA Bus
    3. 11.3 Address Pointer and Transfer Control
    4. 11.4 Pipeline Timing and Throughput
    5. 11.5 CPU and CLA Arbitration
    6. 11.6 Channel Priority
      1. 11.6.1 Round-Robin Mode
      2. 11.6.2 Channel 1 High-Priority Mode
    7. 11.7 Overrun Detection Feature
    8. 11.8 Software
      1. 11.8.1 DMA Examples
        1. 11.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 11.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 11.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 11.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
        5. 11.8.1.5 DMA Transfer Shared Peripheral - C28X_DUAL
    9. 11.9 DMA Registers
      1. 11.9.1 DMA Base Address Table (C28)
      2. 11.9.2 DMA_REGS Registers
      3. 11.9.3 DMA_CH_REGS Registers
      4. 11.9.4 DMA Registers to Driverlib Functions
  14. 12External Memory Interface (EMIF)
    1. 12.1 Introduction
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 EMIF Related Collateral
      3. 12.1.3 Features
        1. 12.1.3.1 Asynchronous Memory Support
        2. 12.1.3.2 Synchronous DRAM Memory Support
      4. 12.1.4 Functional Block Diagram
      5. 12.1.5 Configuring Device Pins
    2. 12.2 EMIF Module Architecture
      1. 12.2.1  EMIF Clock Control
      2. 12.2.2  EMIF Requests
      3. 12.2.3  EMIF Signal Descriptions
      4. 12.2.4  EMIF Signal Multiplexing Control
      5. 12.2.5  SDRAM Controller and Interface
        1. 12.2.5.1  SDRAM Commands
        2. 12.2.5.2  Interfacing to SDRAM
        3. 12.2.5.3  SDRAM Configuration Registers
        4. 12.2.5.4  SDRAM Auto-Initialization Sequence
        5. 12.2.5.5  SDRAM Configuration Procedure
        6. 12.2.5.6  EMIF Refresh Controller
          1. 12.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 12.2.5.7  Self-Refresh Mode
        8. 12.2.5.8  Power-Down Mode
        9. 12.2.5.9  SDRAM Read Operation
        10. 12.2.5.10 SDRAM Write Operations
        11. 12.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 12.2.6  Asynchronous Controller and Interface
        1. 12.2.6.1 Interfacing to Asynchronous Memory
        2. 12.2.6.2 Accessing Larger Asynchronous Memories
        3. 12.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 12.2.6.4 Read and Write Operations in Normal Mode
          1. 12.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 12.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 12.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 12.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 12.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 12.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 12.2.7  Data Bus Parking
      8. 12.2.8  Reset and Initialization Considerations
      9. 12.2.9  Interrupt Support
        1. 12.2.9.1 Interrupt Events
      10. 12.2.10 DMA Event Support
      11. 12.2.11 EMIF Signal Multiplexing
      12. 12.2.12 Memory Map
      13. 12.2.13 Priority and Arbitration
      14. 12.2.14 System Considerations
        1. 12.2.14.1 Asynchronous Request Times
      15. 12.2.15 Power Management
        1. 12.2.15.1 Power Management Using Self-Refresh Mode
        2. 12.2.15.2 Power Management Using Power Down Mode
      16. 12.2.16 Emulation Considerations
    3. 12.3 Example Configuration
      1. 12.3.1 Hardware Interface
      2. 12.3.2 Software Configuration
        1. 12.3.2.1 Configuring the SDRAM Interface
          1. 12.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 12.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 12.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 12.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 12.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 12.3.2.2 Configuring the Flash Interface
          1. 12.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 12.4 Software
      1. 12.4.1 EMIF Examples
        1. 12.4.1.1  Pin setup for EMIF module accessing ASRAM.
        2. 12.4.1.2  EMIF1 ASYNC module accessing 16bit ASRAM.
        3. 12.4.1.3  EMIF1 ASYNC module accessing 16bit ASRAM through CPU1 and CPU2. - C28X_DUAL
        4. 12.4.1.4  EMIF1 ASYNC module accessing 16bit ASRAM trhough CPU1 and CPU2. - C28X_DUAL
        5. 12.4.1.5  EMIF1 module accessing 16bit ASRAM as code memory.
        6. 12.4.1.6  EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
        7. 12.4.1.7  EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power Mode.
        8. 12.4.1.8  EMIF1 module accessing 32bit SDRAM using DMA.
        9. 12.4.1.9  EMIF1 module accessing 16bit SDRAM using alternate address mapping.
        10. 12.4.1.10 EMIF1 ASYNC module accessing 16bit ASRAM HIC FSI
        11. 12.4.1.11 EMIF1 ASYNC module accessing 8bit HIC controller.
    5. 12.5 EMIF Registers
      1. 12.5.1 EMIF Base Address Table (C28)
      2. 12.5.2 EMIF_REGS Registers
      3. 12.5.3 EMIF1_CONFIG_REGS Registers
      4. 12.5.4 EMIF2_CONFIG_REGS Registers
      5. 12.5.5 EMIF Registers to Driverlib Functions
  15. 13Flash Module
    1. 13.1  Introduction to Flash and OTP Memory
      1. 13.1.1 FLASH Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Flash Tools
      4. 13.1.4 Default Flash Configuration
    2. 13.2  Flash Bank, OTP, and Pump
    3. 13.3  Flash Module Controller (FMC)
    4. 13.4  Flash and OTP Memory Power-Down Modes and Wakeup
    5. 13.5  Active Grace Period
    6. 13.6  Flash and OTP Memory Performance
    7. 13.7  Flash Read Interface
      1. 13.7.1 C28x-FMC (CPU1-FMC and CPU2-FMC) Flash Read Interface
        1. 13.7.1.1 Standard Read Mode
        2. 13.7.1.2 Prefetch Mode
          1. 13.7.1.2.1 Data Cache
      2. 13.7.2 M4-FMC (CM-FMC) Flash Read Interface
        1. 13.7.2.1 Standard Read Mode
        2. 13.7.2.2 Cache Mode
          1. 13.7.2.2.1 Program Cache
          2. 13.7.2.2.2 Data Cache
    8. 13.8  Flash Erase and Program
      1. 13.8.1 Erase
      2. 13.8.2 Program
      3. 13.8.3 Verify
    9. 13.9  Error Correction Code (ECC) Protection
      1. 13.9.1 Single-Bit Data Error
      2. 13.9.2 Uncorrectable Error
      3. 13.9.3 SECDED Logic Correctness Check
    10. 13.10 Reserved Locations Within Flash and OTP Memory
    11. 13.11 Migrating an Application from RAM to Flash
    12. 13.12 Procedure to Change the Flash Control Registers
    13. 13.13 Flash Pump Ownership Semaphore
    14. 13.14 Software
      1. 13.14.1 FLASH Examples
        1. 13.14.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - CM
        2. 13.14.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        3. 13.14.1.3 Flash ECC Test Mode
        4. 13.14.1.4 Flash ECC Test Mode - CM
    15. 13.15 Flash Registers
      1. 13.15.1 FLASH Base Address Table (C28)
      2. 13.15.2 CM FLASH Base Address Table (CM)
      3. 13.15.3 FLASH_CTRL_REGS Registers
      4. 13.15.4 FLASH_ECC_REGS Registers
      5. 13.15.5 CM_FLASH_CTRL_REGS Registers
      6. 13.15.6 CM_FLASH_ECC_REGS Registers
      7. 13.15.7 FLASH_PUMP_SEMAPHORE_REGS Registers
      8. 13.15.8 FLASH Registers to Driverlib Functions
  16. 14Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 14.1 Introduction
      1. 14.1.1 ERAD Related Collateral
    2. 14.2 Enhanced Bus Comparator Unit
      1. 14.2.1 Enhanced Bus Comparator Unit Operations
      2. 14.2.2 Event Masking and Exporting
    3. 14.3 System Event Counter Unit
      1. 14.3.1 System Event Counter Modes
        1. 14.3.1.1 Counting Active Levels Versus Edges
        2. 14.3.1.2 Max Mode
        3. 14.3.1.3 Cumulative Mode
        4. 14.3.1.4 Input Signal Selection
      2. 14.3.2 Reset on Event
      3. 14.3.3 Operation Conditions
    4. 14.4 ERAD Ownership, Initialization and Reset
    5. 14.5 ERAD Programming Sequence
      1. 14.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 14.5.2 Timer and Counter Programming Sequence
    6. 14.6 Cyclic Redundancy Check Unit
      1. 14.6.1 CRC Unit Qualifier
      2. 14.6.2 CRC Unit Programming Sequence
    7. 14.7 Program Counter Trace
      1. 14.7.1 Functional Block Diagram
      2. 14.7.2 Trace Qualification Modes
      3. 14.7.3 Trace Memory
      4. 14.7.4 Trace Input Signal Conditioning
      5. 14.7.5 PC Trace Software Operation
      6. 14.7.6 Trace Operation in Debug Mode
    8. 14.8 Software
      1. 14.8.1 ERAD Examples
        1. 14.8.1.1  ERAD Profiling Interrupts
        2. 14.8.1.2  ERAD Profile Function
        3. 14.8.1.3  ERAD Profile Function
        4. 14.8.1.4  ERAD HWBP Monitor Program Counter
        5. 14.8.1.5  ERAD HWBP Monitor Program Counter
        6. 14.8.1.6  ERAD Profile Function
        7. 14.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 14.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 14.8.1.9  ERAD Stack Overflow
        10. 14.8.1.10 ERAD Profile Interrupts CLA
        11. 14.8.1.11 ERAD Profiling Interrupts
        12. 14.8.1.12 ERAD Profiling Interrupts
        13. 14.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 14.8.1.14 ERAD INTERRUPT ORDER
        15. 14.8.1.15 ERAD AND CLB
        16. 14.8.1.16 ERAD PWM PROTECTION
    9. 14.9 ERAD Registers
      1. 14.9.1 ERAD Base Address Table (C28)
      2. 14.9.2 ERAD_GLOBAL_REGS Registers
      3. 14.9.3 ERAD_HWBP_REGS Registers
      4. 14.9.4 ERAD_COUNTER_REGS Registers
      5. 14.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 14.9.6 ERAD_CRC_REGS Registers
      7. 14.9.7 ERAD Registers to Driverlib Functions
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital General-Purpose I/O Control
    4. 15.4  Input Qualification
      1. 15.4.1 No Synchronization (Asynchronous Input)
      2. 15.4.2 Synchronization to SYSCLKOUT Only
      3. 15.4.3 Qualification Using a Sampling Window
    5. 15.5  USB Signals
    6. 15.6  SPI Signals
    7. 15.7  GPIO and Peripheral Muxing
      1. 15.7.1 GPIO Muxing
      2. 15.7.2 Peripheral Muxing
    8. 15.8  Internal Pullup Configuration Requirements
    9. 15.9  Software
      1. 15.9.1 GPIO Examples
        1. 15.9.1.1 Device GPIO Setup
        2. 15.9.1.2 Device GPIO Toggle
        3. 15.9.1.3 Device GPIO Interrupt
      2. 15.9.2 LED Examples
        1. 15.9.2.1 LED Blinky Example (CM) - C28X_CM
        2. 15.9.2.2 LED Blinky Example - C28X_DUAL
        3. 15.9.2.3 LED Blinky Example - C28X_CM
        4. 15.9.2.4 LED Blinky Example with DCSM
        5. 15.9.2.5 LED Blinky Example - C28X_DUAL
    10. 15.10 GPIO Registers
      1. 15.10.1 GPIO Base Address Table (C28)
      2. 15.10.2 CM GPIO Base Address Table (CM)
      3. 15.10.3 GPIO_CTRL_REGS Registers
      4. 15.10.4 GPIO_DATA_REGS Registers
      5. 15.10.5 GPIO_DATA_READ_REGS Registers
      6. 15.10.6 CM_GPIO_DATA_REGS Registers
      7. 15.10.7 CM_GPIO_DATA_READ_REGS Registers
      8. 15.10.8 GPIO Registers to Driverlib Functions
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 Message RAMs
    3. 16.3 IPC Flags and Interrupts
    4. 16.4 IPC Command Registers
    5. 16.5 Free-Running Counter
    6. 16.6 IPC Communication Protocol
    7. 16.7 Software
      1. 16.7.1 IPC Examples
        1. 16.7.1.1  IPC basic message passing example with interrupt - C28X_CM
        2. 16.7.1.2  IPC basic message passing example with interrupt - C28X_CM
        3. 16.7.1.3  IPC basic message passing example with interrupt - C28X_DUAL
        4. 16.7.1.4  IPC basic message passing example with interrupt - C28X_DUAL
        5. 16.7.1.5  IPC message passing example with interrupt and message queue - C28X_CM
        6. 16.7.1.6  IPC message passing example with interrupt and message queue - C28X_CM
        7. 16.7.1.7  IPC message passing example with interrupt and message queue - C28X_DUAL
        8. 16.7.1.8  IPC message passing example with interrupt and message queue - C28X_DUAL
        9. 16.7.1.9  IPC basic message passing example with interrupt - C28X_DUAL
        10. 16.7.1.10 IPC basic message passing example with interrupt - C28X_DUAL
        11. 16.7.1.11 IPC message passing example with interrupt and message queue - C28X_DUAL
        12. 16.7.1.12 IPC message passing example with interrupt and message queue - C28X_DUAL
    8. 16.8 IPC Registers
      1. 16.8.1 IPC Base Address Table (C28)
      2. 16.8.2 CM IPC Base Address Table (CM)
      3. 16.8.3 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      4. 16.8.4 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      5. 16.8.5 CPU1TOCM_IPC_REGS_CPU1VIEW Registers
      6. 16.8.6 CPU1TOCM_IPC_REGS_CMVIEW Registers
      7. 16.8.7 CPU2TOCM_IPC_REGS_CPU2VIEW Registers
      8. 16.8.8 CPU2TOCM_IPC_REGS_CMVIEW Registers
      9. 16.8.9 IPC Registers to Driverlib Functions
  19. 17Crossbar (X-BAR)
    1. 17.1 Input X-BAR and CLB Input X-BAR
      1. 17.1.1 CLB Input X-BAR
    2. 17.2 ePWM, CLB, and GPIO Output X-BAR
      1. 17.2.1 ePWM X-BAR
        1. 17.2.1.1 ePWM X-BAR Architecture
      2. 17.2.2 CLB X-BAR
        1. 17.2.2.1 CLB X-BAR Architecture
      3. 17.2.3 GPIO Output X-BAR
        1. 17.2.3.1 GPIO Output X-BAR Architecture
      4. 17.2.4 CLB Output X-BAR
        1. 17.2.4.1 CLB Output X-BAR Architecture
      5. 17.2.5 X-BAR Flags
    3. 17.3 XBAR Registers
      1. 17.3.1 XBAR Base Address Table (C28)
      2. 17.3.2 INPUT_XBAR_REGS Registers
      3. 17.3.3 XBAR_REGS Registers
      4. 17.3.4 EPWM_XBAR_REGS Registers
      5. 17.3.5 CLB_XBAR_REGS Registers
      6. 17.3.6 OUTPUT_XBAR_REGS Registers
      7. 17.3.7 Register to Driverlib Function Mapping
        1. 17.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 17.3.7.2 XBAR Registers to Driverlib Functions
        3. 17.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 17.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 17.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  20. 18â–º ANALOG PERIPHERALS
    1. 18.1 Technical Reference Manual Overview
  21. 19Analog Subsystem
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 Optimizing Power-Up Time
    3. 19.3 Analog Subsystem Registers
      1. 19.3.1 ASBSYS Base Address Table (C28)
      2. 19.3.2 ANALOG_SUBSYS_REGS Registers
  22. 20Analog-to-Digital Converter (ADC)
    1. 20.1  Introduction
      1. 20.1.1 ADC Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2  ADC Configurability
      1. 20.2.1 Clock Configuration
      2. 20.2.2 Resolution
      3. 20.2.3 Voltage Reference
        1. 20.2.3.1 External Reference Mode
      4. 20.2.4 Signal Mode
      5. 20.2.5 Expected Conversion Results
      6. 20.2.6 Interpreting Conversion Results
    3. 20.3  SOC Principle of Operation
      1. 20.3.1 SOC Configuration
      2. 20.3.2 Trigger Operation
      3. 20.3.3 ADC Acquisition (Sample and Hold) Window
      4. 20.3.4 ADC Input Models
      5. 20.3.5 Channel Selection
    4. 20.4  SOC Configuration Examples
      1. 20.4.1 Single Conversion from ePWM Trigger
      2. 20.4.2 Oversampled Conversion from ePWM Trigger
      3. 20.4.3 Multiple Conversions from CPU Timer Trigger
      4. 20.4.4 Software Triggering of SOCs
    5. 20.5  ADC Conversion Priority
    6. 20.6  Burst Mode
      1. 20.6.1 Burst Mode Example
      2. 20.6.2 Burst Mode Priority Example
    7. 20.7  EOC and Interrupt Operation
      1. 20.7.1 Interrupt Overflow
      2. 20.7.2 Continue to Interrupt Mode
      3. 20.7.3 Early Interrupt Configuration Mode
    8. 20.8  Post-Processing Blocks
      1. 20.8.1 PPB Offset Correction
      2. 20.8.2 PPB Error Calculation
      3. 20.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 20.8.4 PPB Sample Delay Capture
    9. 20.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 20.9.1 Implementation
      2. 20.9.2 Detecting an Open Input Pin
      3. 20.9.3 Detecting a Shorted Input Pin
    10. 20.10 Power-Up Sequence
    11. 20.11 ADC Calibration
      1. 20.11.1 ADC Zero Offset Calibration
      2. 20.11.2 ADC Calibration Routines in OTP Memory
    12. 20.12 ADC Timings
      1. 20.12.1 ADC Timing Diagrams
    13. 20.13 Additional Information
      1. 20.13.1 Ensuring Synchronous Operation
        1. 20.13.1.1 Basic Synchronous Operation
        2. 20.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 20.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 20.13.1.4 Synchronous Operation with Different Resolutions
        5. 20.13.1.5 Non-overlapping Conversions
      2. 20.13.2 Choosing an Acquisition Window Duration
      3. 20.13.3 Achieving Simultaneous Sampling
      4. 20.13.4 Result Register Mapping
      5. 20.13.5 Internal Temperature Sensor
      6. 20.13.6 Designing an External Reference Circuit
    14. 20.14 Software
      1. 20.14.1 ADC Examples
        1. 20.14.1.1  ADC Software Triggering
        2. 20.14.1.2  ADC ePWM Triggering
        3. 20.14.1.3  ADC Temperature Sensor Conversion
        4. 20.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 20.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 20.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 20.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 20.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 20.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 20.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 20.14.1.11 ADC Burst Mode
        12. 20.14.1.12 ADC Burst Mode Oversampling
        13. 20.14.1.13 ADC SOC Oversampling
        14. 20.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 20.14.1.15 ADC High Priority SOC (adc_high_priority_soc)
        16. 20.14.1.16 ADC Interleaved Averaging in Software
        17. 20.14.1.17 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 20.15 ADC Registers
      1. 20.15.1 ADC Base Address Table (C28)
      2. 20.15.2 ADC_REGS Registers
      3. 20.15.3 ADC_RESULT_REGS Registers
      4. 20.15.4 ADC Registers to Driverlib Functions
  23. 21Buffered Digital-to-Analog Converter (DAC)
    1. 21.1 Introduction
      1. 21.1.1 DAC Related Collateral
      2. 21.1.2 Features
      3. 21.1.3 Block Diagram
    2. 21.2 Using the DAC
      1. 21.2.1 Initialization Sequence
      2. 21.2.2 DAC Offset Adjustment
      3. 21.2.3 EPWMSYNCPER Signal
    3. 21.3 Lock Registers
    4. 21.4 Software
      1. 21.4.1 DAC Examples
        1. 21.4.1.1 Buffered DAC Enable
        2. 21.4.1.2 Buffered DAC Random
        3. 21.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 21.5 DAC Registers
      1. 21.5.1 DAC Base Address Table (C28)
      2. 21.5.2 DAC_REGS Registers
      3. 21.5.3 DAC Registers to Driverlib Functions
  24. 22Comparator Subsystem (CMPSS)
    1. 22.1 Introduction
      1. 22.1.1 CMPSS Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Block Diagram
    2. 22.2 Comparator
    3. 22.3 Reference DAC
    4. 22.4 Ramp Generator
      1. 22.4.1 Ramp Generator Overview
      2. 22.4.2 Ramp Generator Behavior
      3. 22.4.3 Ramp Generator Behavior at Corner Cases
    5. 22.5 Digital Filter
      1. 22.5.1 Filter Initialization Sequence
    6. 22.6 Using the CMPSS
      1. 22.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 22.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 22.6.3 Calibrating the CMPSS
      4. 22.6.4 Enabling and Disabling the CMPSS Clock
    7. 22.7 Software
      1. 22.7.1 CMPSS Examples
        1. 22.7.1.1 CMPSS Asynchronous Trip
        2. 22.7.1.2 CMPSS Digital Filter Configuration
    8. 22.8 CMPSS Registers
      1. 22.8.1 CMPSS Base Address Table (C28)
      2. 22.8.2 CMPSS_REGS Registers
      3. 22.8.3 CMPSS Registers to Driverlib Functions
  25. 23â–º CONTROL PERIPHERALS
    1. 23.1 Technical Reference Manual Overview
  26. 24Enhanced Capture (eCAP)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 ECAP Related Collateral
    2. 24.2 Description
    3. 24.3 Configuring Device Pins for the eCAP
    4. 24.4 Capture and APWM Operating Mode
    5. 24.5 Capture Mode Description
      1. 24.5.1  Event Prescaler
      2. 24.5.2  Edge Polarity Select and Qualifier
      3. 24.5.3  Continuous/One-Shot Control
      4. 24.5.4  32-Bit Counter and Phase Control
      5. 24.5.5  CAP1-CAP4 Registers
      6. 24.5.6  eCAP Synchronization
        1. 24.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 24.5.7  Interrupt Control
      8. 24.5.8  DMA Interrupt
      9. 24.5.9  Shadow Load and Lockout Control
      10. 24.5.10 APWM Mode Operation
    6. 24.6 Application of the eCAP Module
      1. 24.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 24.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 24.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 24.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 24.7 Application of the APWM Mode
      1. 24.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 24.8 Software
      1. 24.8.1 ECAP Examples
        1. 24.8.1.1 eCAP APWM Example
        2. 24.8.1.2 eCAP Capture PWM Example
        3. 24.8.1.3 eCAP APWM Phase-shift Example
        4. 24.8.1.4 eCAP Software Sync Example
    9. 24.9 eCAP Registers
      1. 24.9.1 ECAP Base Address Table (C28)
      2. 24.9.2 ECAP_REGS Registers
      3. 24.9.3 ECAP Registers to Driverlib Functions
  27. 25High Resolution Capture (HRCAP)
    1. 25.1 Introduction
      1. 25.1.1 HRCAP Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Description
    2. 25.2 Operational Details
      1. 25.2.1 HRCAP Clocking
      2. 25.2.2 HRCAP Initialization Sequence
      3. 25.2.3 HRCAP Interrupts
      4. 25.2.4 HRCAP Calibration
        1. 25.2.4.1 Applying the Scale Factor
    3. 25.3 Known Exceptions
    4. 25.4 Software
      1. 25.4.1 HRCAP Examples
        1. 25.4.1.1 HRCAP Capture and Calibration Example
    5. 25.5 HRCAP Registers
      1. 25.5.1 HRCAP Base Address Table (C28)
      2. 25.5.2 HRCAP_REGS Registers
      3. 25.5.3 HRCAP Registers to Driverlib Functions
  28. 26Enhanced Pulse Width Modulator (ePWM)
    1. 26.1  Introduction
      1. 26.1.1 EPWM Related Collateral
      2. 26.1.2 Submodule Overview
    2. 26.2  Configuring Device Pins
    3. 26.3  ePWM Modules Overview
    4. 26.4  Time-Base (TB) Submodule
      1. 26.4.1 Purpose of the Time-Base Submodule
      2. 26.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 26.4.3 Calculating PWM Period and Frequency
        1. 26.4.3.1 Time-Base Period Shadow Register
        2. 26.4.3.2 Time-Base Clock Synchronization
        3. 26.4.3.3 Time-Base Counter Synchronization
        4. 26.4.3.4 ePWM SYNC Selection
      4. 26.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 26.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 26.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 26.4.7 Global Load
        1. 26.4.7.1 Global Load Pulse Pre-Scalar
        2. 26.4.7.2 One-Shot Load Mode
        3. 26.4.7.3 One-Shot Sync Mode
    5. 26.5  Counter-Compare (CC) Submodule
      1. 26.5.1 Purpose of the Counter-Compare Submodule
      2. 26.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 26.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 26.5.4 Count Mode Timing Waveforms
    6. 26.6  Action-Qualifier (AQ) Submodule
      1. 26.6.1 Purpose of the Action-Qualifier Submodule
      2. 26.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 26.6.3 Action-Qualifier Event Priority
      4. 26.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 26.6.5 Configuration Requirements for Common Waveforms
    7. 26.7  Dead-Band Generator (DB) Submodule
      1. 26.7.1 Purpose of the Dead-Band Submodule
      2. 26.7.2 Dead-band Submodule Additional Operating Modes
      3. 26.7.3 Operational Highlights for the Dead-Band Submodule
    8. 26.8  PWM Chopper (PC) Submodule
      1. 26.8.1 Purpose of the PWM Chopper Submodule
      2. 26.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 26.8.3 Waveforms
        1. 26.8.3.1 One-Shot Pulse
        2. 26.8.3.2 Duty Cycle Control
    9. 26.9  Trip-Zone (TZ) Submodule
      1. 26.9.1 Purpose of the Trip-Zone Submodule
      2. 26.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 26.9.2.1 Trip-Zone Configurations
      3. 26.9.3 Generating Trip Event Interrupts
    10. 26.10 Event-Trigger (ET) Submodule
      1. 26.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 26.11 Digital Compare (DC) Submodule
      1. 26.11.1 Purpose of the Digital Compare Submodule
      2. 26.11.2 Enhanced Trip Action Using CMPSS
      3. 26.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 26.11.4 Operation Highlights of the Digital Compare Submodule
        1. 26.11.4.1 Digital Compare Events
        2. 26.11.4.2 Event Filtering
        3. 26.11.4.3 Valley Switching
    12. 26.12 ePWM Crossbar (X-BAR)
    13. 26.13 Applications to Power Topologies
      1. 26.13.1  Overview of Multiple Modules
      2. 26.13.2  Key Configuration Capabilities
      3. 26.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 26.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 26.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 26.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 26.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 26.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 26.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 26.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 26.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 26.14 Register Lock Protection
    15. 26.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 26.15.1 Operational Description of HRPWM
        1. 26.15.1.1 Controlling the HRPWM Capabilities
        2. 26.15.1.2 HRPWM Source Clock
        3. 26.15.1.3 Configuring the HRPWM
        4. 26.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 26.15.1.5 Principle of Operation
          1. 26.15.1.5.1 Edge Positioning
          2. 26.15.1.5.2 Scaling Considerations
          3. 26.15.1.5.3 Duty Cycle Range Limitation
          4. 26.15.1.5.4 High-Resolution Period
            1. 26.15.1.5.4.1 High-Resolution Period Configuration
        6. 26.15.1.6 Deadband High-Resolution Operation
        7. 26.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 26.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 26.15.1.8.1 #Defines for HRPWM Header Files
          2. 26.15.1.8.2 Implementing a Simple Buck Converter
            1. 26.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 26.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 26.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 26.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 26.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 26.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 26.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 26.15.2.2 Software Usage
          1. 26.15.2.2.1 A Sample of How to Add "Include" Files
          2.        1176
          3. 26.15.2.2.2 Declaring an Element
          4.        1178
          5. 26.15.2.2.3 Initializing With a Scale Factor Value
          6.        1180
          7. 26.15.2.2.4 SFO Function Calls
    16. 26.16 Software
      1. 26.16.1 EPWM Examples
        1. 26.16.1.1  ePWM Trip Zone
        2. 26.16.1.2  ePWM Up Down Count Action Qualifier
        3. 26.16.1.3  ePWM Synchronization
        4. 26.16.1.4  ePWM Digital Compare
        5. 26.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 26.16.1.6  ePWM Valley Switching
        7. 26.16.1.7  ePWM Digital Compare Edge Filter
        8. 26.16.1.8  ePWM Deadband
        9. 26.16.1.9  ePWM DMA
        10. 26.16.1.10 ePWM Chopper
        11. 26.16.1.11 EPWM Configure Signal
        12. 26.16.1.12 Realization of Monoshot mode
        13. 26.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 26.16.2 HRPWM Examples
        1. 26.16.2.1 HRPWM Duty Control with SFO
        2. 26.16.2.2 HRPWM Slider
        3. 26.16.2.3 HRPWM Period Control
        4. 26.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 26.16.2.5 HRPWM Slider Test
        6. 26.16.2.6 HRPWM Duty Up Count
        7. 26.16.2.7 HRPWM Period Up-Down Count
    17. 26.17 ePWM Registers
      1. 26.17.1 EPWM Base Address Table (C28)
      2. 26.17.2 EPWM_REGS Registers
      3. 26.17.3 SYNC_SOC_REGS Registers
      4. 26.17.4 Register to Driverlib Function Mapping
        1. 26.17.4.1 EPWM Registers to Driverlib Functions
        2. 26.17.4.2 HRPWM Registers to Driverlib Functions
  29. 27Enhanced Quadrature Encoder Pulse (eQEP)
    1. 27.1  Introduction
      1. 27.1.1 EQEP Related Collateral
    2. 27.2  Configuring Device Pins
    3. 27.3  Description
      1. 27.3.1 EQEP Inputs
      2. 27.3.2 Functional Description
      3. 27.3.3 eQEP Memory Map
    4. 27.4  Quadrature Decoder Unit (QDU)
      1. 27.4.1 Position Counter Input Modes
        1. 27.4.1.1 Quadrature Count Mode
        2. 27.4.1.2 Direction-Count Mode
        3. 27.4.1.3 Up-Count Mode
        4. 27.4.1.4 Down-Count Mode
      2. 27.4.2 eQEP Input Polarity Selection
      3. 27.4.3 Position-Compare Sync Output
    5. 27.5  Position Counter and Control Unit (PCCU)
      1. 27.5.1 Position Counter Operating Modes
        1. 27.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 27.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 27.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 27.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 27.5.2 Position Counter Latch
        1. 27.5.2.1 Index Event Latch
        2. 27.5.2.2 Strobe Event Latch
      3. 27.5.3 Position Counter Initialization
      4. 27.5.4 eQEP Position-compare Unit
    6. 27.6  eQEP Edge Capture Unit
    7. 27.7  eQEP Watchdog
    8. 27.8  eQEP Unit Timer Base
    9. 27.9  QMA Module
      1. 27.9.1 Modes of Operation
        1. 27.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 27.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 27.9.2 Interrupt and Error Generation
    10. 27.10 eQEP Interrupt Structure
    11. 27.11 Software
      1. 27.11.1 EQEP Examples
        1. 27.11.1.1 Frequency Measurement Using eQEP
        2. 27.11.1.2 Position and Speed Measurement Using eQEP
        3. 27.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 27.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 27.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 27.12 eQEP Registers
      1. 27.12.1 EQEP Base Address Table (C28)
      2. 27.12.2 EQEP_REGS Registers
      3. 27.12.3 EQEP Registers to Driverlib Functions
  30. 28Sigma Delta Filter Module (SDFM)
    1. 28.1  Introduction
      1. 28.1.1 SDFM Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Block Diagram
    2. 28.2  Configuring Device Pins
    3. 28.3  Input Qualification
    4. 28.4  Input Control Unit
    5. 28.5  SDFM Clock Control
    6. 28.6  Sinc Filter
      1. 28.6.1 Data Rate and Latency of the Sinc Filter
    7. 28.7  Data (Primary) Filter Unit
      1. 28.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 28.7.2 Data FIFO
      3. 28.7.3 SDSYNC Event
    8. 28.8  Comparator (Secondary) Filter Unit
      1. 28.8.1 Higher Threshold (HLT) Comparators
      2. 28.8.2 Lower Threshold (LLT) Comparators
      3. 28.8.3 Digital Filter
    9. 28.9  Theoretical SDFM Filter Output
    10. 28.10 Interrupt Unit
      1. 28.10.1 SDFM (SDyERR) Interrupt Sources
      2. 28.10.2 Data Ready (DRINT) Interrupt Sources
    11. 28.11 Software
      1. 28.11.1 SDFM Examples
        1. 28.11.1.1 SDFM Filter Sync CPU
        2. 28.11.1.2 SDFM Filter Sync CLA
        3. 28.11.1.3 SDFM Filter Sync DMA
        4. 28.11.1.4 SDFM PWM Sync
        5. 28.11.1.5 SDFM Type 1 Filter FIFO
        6. 28.11.1.6 SDFM Filter Sync CLA
    12. 28.12 SDFM Registers
      1. 28.12.1 SDFM Base Address Table (C28)
      2. 28.12.2 SDFM_REGS Registers
      3. 28.12.3 SDFM Registers to Driverlib Functions
  31. 29â–º COMMUNICATION PERIPHERALS
    1. 29.1 Technical Reference Manual Overview
  32. 30Controller Area Network (CAN)
    1. 30.1  Introduction
      1. 30.1.1 DCAN Related Collateral
      2. 30.1.2 Features
      3. 30.1.3 Block Diagram
        1. 30.1.3.1 CAN Core
        2. 30.1.3.2 Message Handler
        3. 30.1.3.3 Message RAM
        4. 30.1.3.4 Registers and Message Object Access (IFx)
    2. 30.2  Functional Description
      1. 30.2.1 Configuring Device Pins
      2. 30.2.2 Address/Data Bus Bridge
    3. 30.3  Operating Modes
      1. 30.3.1 Initialization
      2. 30.3.2 CAN Message Transfer (Normal Operation)
        1. 30.3.2.1 Disabled Automatic Retransmission
        2. 30.3.2.2 Auto-Bus-On
      3. 30.3.3 Test Modes
        1. 30.3.3.1 Silent Mode
        2. 30.3.3.2 Loopback Mode
        3. 30.3.3.3 External Loopback Mode
        4. 30.3.3.4 Loopback Combined with Silent Mode
    4. 30.4  Multiple Clock Source
    5. 30.5  Interrupt Functionality
      1. 30.5.1 Message Object Interrupts
      2. 30.5.2 Status Change Interrupts
      3. 30.5.3 Error Interrupts
      4. 30.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 30.5.5 Interrupt Topologies
    6. 30.6  DMA Functionality
    7. 30.7  Parity Check Mechanism
      1. 30.7.1 Behavior on Parity Error
    8. 30.8  Debug Mode
    9. 30.9  Module Initialization
    10. 30.10 Configuration of Message Objects
      1. 30.10.1 Configuration of a Transmit Object for Data Frames
      2. 30.10.2 Configuration of a Transmit Object for Remote Frames
      3. 30.10.3 Configuration of a Single Receive Object for Data Frames
      4. 30.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 30.10.5 Configuration of a FIFO Buffer
    11. 30.11 Message Handling
      1. 30.11.1  Message Handler Overview
      2. 30.11.2  Receive/Transmit Priority
      3. 30.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 30.11.4  Updating a Transmit Object
      5. 30.11.5  Changing a Transmit Object
      6. 30.11.6  Acceptance Filtering of Received Messages
      7. 30.11.7  Reception of Data Frames
      8. 30.11.8  Reception of Remote Frames
      9. 30.11.9  Reading Received Messages
      10. 30.11.10 Requesting New Data for a Receive Object
      11. 30.11.11 Storing Received Messages in FIFO Buffers
      12. 30.11.12 Reading from a FIFO Buffer
    12. 30.12 CAN Bit Timing
      1. 30.12.1 Bit Time and Bit Rate
        1. 30.12.1.1 Synchronization Segment
        2. 30.12.1.2 Propagation Time Segment
        3. 30.12.1.3 Phase Buffer Segments and Synchronization
        4. 30.12.1.4 Oscillator Tolerance Range
      2. 30.12.2 Configuration of the CAN Bit Timing
        1. 30.12.2.1 Calculation of the Bit Timing Parameters
        2. 30.12.2.2 Example for Bit Timing at High Baudrate
        3. 30.12.2.3 Example for Bit Timing at Low Baudrate
    13. 30.13 Message Interface Register Sets
      1. 30.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 30.13.2 Message Interface Register Set 3 (IF3)
    14. 30.14 Message RAM
      1. 30.14.1 Structure of Message Objects
      2. 30.14.2 Addressing Message Objects in RAM
      3. 30.14.3 Message RAM Representation in Debug Mode
    15. 30.15 Software
      1. 30.15.1 CAN Examples
        1. 30.15.1.1  NMI handling - C28X_DUAL
        2. 30.15.1.2  CAN External Loopback
        3. 30.15.1.3  Watchdog Reset - C28X_DUAL
        4. 30.15.1.4  CAN Loopback - CM
        5. 30.15.1.5  CAN External Loopback with Interrupts
        6. 30.15.1.6  CAN External Loopback with Interrupts - C28X_DUAL
        7. 30.15.1.7  CAN External Loopback with Interrupts - CM
        8. 30.15.1.8  CAN-A to CAN-B External Transmit
        9. 30.15.1.9  CAN-A to CAN-B External Transmit - CM
        10. 30.15.1.10 CAN External Loopback with DMA
        11. 30.15.1.11 CAN Transmit and Receive Configurations - CM
        12. 30.15.1.12 CAN Transmit and Receive Configurations
        13. 30.15.1.13 CAN Error Generation Example
        14. 30.15.1.14 CAN Remote Request Loopback
        15. 30.15.1.15 CAN example that illustrates the usage of Mask registers
    16. 30.16 CAN Registers
      1. 30.16.1 CAN Base Address Table (C28)
      2. 30.16.2 CM CAN Base Address Table (CM)
      3. 30.16.3 CAN_REGS Registers
      4. 30.16.4 CAN Registers to Driverlib Functions
  33. 31EtherCAT® Slave Controller (ESC)
    1. 31.1 Introduction
      1. 31.1.1  ECAT Related Collateral
      2. 31.1.2  ESC Features
      3. 31.1.3  ESC Subsystem Integrated Features
      4. 31.1.4  F2838x ESC versus Beckhoff ET1100
      5. 31.1.5  EtherCAT IP Block Diagram
      6. 31.1.6  ESC Functional Blocks
        1. 31.1.6.1  Interface to EtherCAT Master
        2. 31.1.6.2  Process Data Interface
        3. 31.1.6.3  General-Purpose Inputs and Outputs
        4. 31.1.6.4  EtherCAT Processing Unit (EPU)
        5. 31.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 31.1.6.6  Sync Manager
        7. 31.1.6.7  Monitoring
        8. 31.1.6.8  Reset Controller
        9. 31.1.6.9  PHY Management
        10. 31.1.6.10 Distributed Clock (DC)
        11. 31.1.6.11 EEPROM
        12. 31.1.6.12 Status / LEDs
      7. 31.1.7  EtherCAT Physical Layer
        1. 31.1.7.1 MII Interface
        2. 31.1.7.2 PHY Management Interface
          1. 31.1.7.2.1 PHY Address Configuration
          2. 31.1.7.2.2 PHY Reset Signal
          3. 31.1.7.2.3 PHY Clock
      8. 31.1.8  EtherCAT Protocol
      9. 31.1.9  EtherCAT State Machine (ESM)
      10. 31.1.10 More Information on EtherCAT
      11. 31.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 31.2 ESC and ESCSS Description
      1. 31.2.1  ESC RAM Parity and Memory Address Maps
        1. 31.2.1.1 ESC RAM Parity Logic
        2. 31.2.1.2 CPU1 ESC Memory Address Map
        3. 31.2.1.3 CM ESC Memory Address Map
      2. 31.2.2  Local Host Communication
        1. 31.2.2.1 Byte Accessibility Through PDI
        2. 31.2.2.2 Software Details for Operation Across Clock Domains
      3. 31.2.3  Debug Emulation Mode Operation
      4. 31.2.4  ESC SubSystem
        1. 31.2.4.1 CPU1 Bus Interface
        2. 31.2.4.2 CM Bus Interface
      5. 31.2.5  Interrupts and Interrupt Mapping
      6. 31.2.6  Power, Clocks, and Resets
        1. 31.2.6.1 Power
        2. 31.2.6.2 Clocking
        3. 31.2.6.3 Resets
          1. 31.2.6.3.1 Chip-Level Reset
          2. 31.2.6.3.2 EtherCAT Soft Resets
          3. 31.2.6.3.3 Reset Out (RESET_OUT)
      7. 31.2.7  LED Controls
      8. 31.2.8  Slave Node Configuration and EEPROM
      9. 31.2.9  General-Purpose Inputs and Outputs
        1. 31.2.9.1 General-Purpose Inputs
        2. 31.2.9.2 General-Purpose Output
      10. 31.2.10 Distributed Clocks – Sync and Latch
        1. 31.2.10.1 Clock Synchronization
        2. 31.2.10.2 SYNC Signals
          1. 31.2.10.2.1 Seeking Host Intervention
        3. 31.2.10.3 LATCH Signals
          1. 31.2.10.3.1 Timestamping
        4. 31.2.10.4 Device Control and Synchronization
          1. 31.2.10.4.1 Synchronization of PWM
          2. 31.2.10.4.2 ECAP SYNC Inputs
          3. 31.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 31.3 Software Initialization Sequence and Allocating Ownership
    4. 31.4 ESC Configuration Constants
    5. 31.5 EtherCAT IP Registers
      1. 31.5.1 ECAT Base Address Table (C28)
      2. 31.5.2 ESCSS_REGS Registers
      3. 31.5.3 ESCSS_CONFIG_REGS Registers
      4. 31.5.4 ESC_SS Registers to Driverlib Functions
  34. 32Fast Serial Interface (FSI)
    1. 32.1 Introduction
      1. 32.1.1 FSI Related Collateral
      2. 32.1.2 FSI Features
    2. 32.2 System-level Integration
      1. 32.2.1 CPU Interface
      2. 32.2.2 Signal Description
        1. 32.2.2.1 Configuring Device Pins
      3. 32.2.3 FSI Interrupts
        1. 32.2.3.1 Transmitter Interrupts
        2. 32.2.3.2 Receiver Interrupts
        3. 32.2.3.3 Configuring Interrupts
        4. 32.2.3.4 Handling Interrupts
      4. 32.2.4 CLA Task Triggering
      5. 32.2.5 DMA Interface
      6. 32.2.6 External Frame Trigger Mux
    3. 32.3 FSI Functional Description
      1. 32.3.1  Introduction to Operation
      2. 32.3.2  FSI Transmitter Module
        1. 32.3.2.1 Initialization
        2. 32.3.2.2 FSI_TX Clocking
        3. 32.3.2.3 Transmitting Frames
          1. 32.3.2.3.1 Software Triggered Frames
          2. 32.3.2.3.2 Externally Triggered Frames
          3. 32.3.2.3.3 Ping Frame Generation
            1. 32.3.2.3.3.1 Automatic Ping Frames
            2. 32.3.2.3.3.2 Software Triggered Ping Frame
            3. 32.3.2.3.3.3 Externally Triggered Ping Frame
          4. 32.3.2.3.4 Transmitting Frames with DMA
        4. 32.3.2.4 Transmit Buffer Management
        5. 32.3.2.5 CRC Submodule
        6. 32.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 32.3.2.7 Reset
      3. 32.3.3  FSI Receiver Module
        1. 32.3.3.1  Initialization
        2. 32.3.3.2  FSI_RX Clocking
        3. 32.3.3.3  Receiving Frames
          1. 32.3.3.3.1 Receiving Frames with DMA
        4. 32.3.3.4  Ping Frame Watchdog
        5. 32.3.3.5  Frame Watchdog
        6. 32.3.3.6  Delay Line Control
        7. 32.3.3.7  Buffer Management
        8. 32.3.3.8  CRC Submodule
        9. 32.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 32.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 32.3.3.11 FSI_RX Reset
      4. 32.3.4  Frame Format
        1. 32.3.4.1 FSI Frame Phases
        2. 32.3.4.2 Frame Types
          1. 32.3.4.2.1 Ping Frames
          2. 32.3.4.2.2 Error Frames
          3. 32.3.4.2.3 Data Frames
        3. 32.3.4.3 Multi-Lane Transmission
      5. 32.3.5  Flush Sequence
      6. 32.3.6  Internal Loopback
      7. 32.3.7  CRC Generation
      8. 32.3.8  ECC Module
      9. 32.3.9  Tag Matching
      10. 32.3.10 TDM Configurations
      11. 32.3.11 FSI-SPI Compatibility Mode
        1. 32.3.11.1 Available SPI Modes
          1. 32.3.11.1.1 FSITX as SPI Master, Transmit Only
            1. 32.3.11.1.1.1 Initialization
            2. 32.3.11.1.1.2 Operation
          2. 32.3.11.1.2 FSIRX as SPI Slave, Receive Only
            1. 32.3.11.1.2.1 Initialization
            2. 32.3.11.1.2.2 Operation
          3. 32.3.11.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 32.3.11.1.3.1 Initialization
            2. 32.3.11.1.3.2 Operation
    4. 32.4 FSI Programing Guide
      1. 32.4.1 Establishing the Communication Link
        1. 32.4.1.1 Establishing the Communication Link from the Master Device
        2. 32.4.1.2 Establishing the Communication Link from the Slave Device
      2. 32.4.2 Register Protection
      3. 32.4.3 Emulation Mode
    5. 32.5 Software
      1. 32.5.1 FSI Examples
        1. 32.5.1.1  FSI Multi-Rx Tag-Match - C28X_DUAL
        2. 32.5.1.2  FSI Loopback:CPU Control
        3. 32.5.1.3  FSI Multi-Rx Tag-Match - C28X_DUAL
        4. 32.5.1.4  FSI Loopback CLA control
        5. 32.5.1.5  FSI DMA frame transfers:DMA Control
        6. 32.5.1.6  FSI data transfer by external trigger
        7. 32.5.1.7  FSI data transfers upon CPU Timer event
        8. 32.5.1.8  FSI and SPI communication(fsi_ex6_spi_main_tx)
        9. 32.5.1.9  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        10. 32.5.1.10 FSI P2Point Connection:Rx Side
        11. 32.5.1.11 FSI P2Point Connection:Tx Side
        12. 32.5.1.12 FSI star connection topology example. FSI communication using CPU control
        13. 32.5.1.13 FSI daisy chain topology, lead device example
        14. 32.5.1.14 FSI daisy chain topology, node device example
    6. 32.6 FSI Registers
      1. 32.6.1 FSI Base Address Table (C28)
      2. 32.6.2 FSI_TX_REGS Registers
      3. 32.6.3 FSI_RX_REGS Registers
      4. 32.6.4 FSI Registers to Driverlib Functions
  35. 33Inter-Integrated Circuit Module (I2C)
    1. 33.1 Introduction
      1. 33.1.1 I2C Related Collateral
      2. 33.1.2 Features
      3. 33.1.3 Features Not Supported
      4. 33.1.4 Functional Overview
      5. 33.1.5 Clock Generation
      6. 33.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 33.1.6.1 Formula for the Master Clock Period
    2. 33.2 Configuring Device Pins
    3. 33.3 I2C Module Operational Details
      1. 33.3.1  Input and Output Voltage Levels
      2. 33.3.2  Selecting Pullup Resistors
      3. 33.3.3  Data Validity
      4. 33.3.4  Operating Modes
      5. 33.3.5  I2C Module START and STOP Conditions
      6. 33.3.6  Non-repeat Mode versus Repeat Mode
      7. 33.3.7  Serial Data Formats
        1. 33.3.7.1 7-Bit Addressing Format
        2. 33.3.7.2 10-Bit Addressing Format
        3. 33.3.7.3 Free Data Format
        4. 33.3.7.4 Using a Repeated START Condition
      8. 33.3.8  Clock Synchronization
      9. 33.3.9  Arbitration
      10. 33.3.10 Digital Loopback Mode
      11. 33.3.11 NACK Bit Generation
    4. 33.4 Interrupt Requests Generated by the I2C Module
      1. 33.4.1 Basic I2C Interrupt Requests
      2. 33.4.2 I2C FIFO Interrupts
    5. 33.5 Resetting or Disabling the I2C Module
    6. 33.6 Software
      1. 33.6.1 I2C Examples
        1. 33.6.1.1  C28x-I2C Library source file for FIFO interrupts
        2. 33.6.1.2  C28x-I2C Library source file for FIFO using polling
        3. 33.6.1.3  C28x-I2C Library source file for FIFO interrupts
        4. 33.6.1.4  I2C Loopback with Slave Receive Interrupt - CM
        5. 33.6.1.5  I2C Digital Loopback with FIFO Interrupts
        6. 33.6.1.6  I2C EEPROM
        7. 33.6.1.7  I2C Digital External Loopback with FIFO Interrupts
        8. 33.6.1.8  I2C EEPROM
        9. 33.6.1.9  I2C controller target communication using FIFO interrupts
        10. 33.6.1.10 I2C EEPROM
    7. 33.7 I2C Registers
      1. 33.7.1 I2C Base Address Table (C28)
      2. 33.7.2 I2C_REGS Registers
      3. 33.7.3 I2C Registers to Driverlib Functions
  36. 34Multichannel Buffered Serial Port (McBSP)
    1. 34.1  Introduction
      1. 34.1.1 MCBSP Related Collateral
      2. 34.1.2 Features of the McBSPs
      3. 34.1.3 McBSP Pins/Signals
        1. 34.1.3.1 McBSP Generic Block Diagram
    2. 34.2  Configuring Device Pins
    3. 34.3  McBSP Operation
      1. 34.3.1 Data Transfer Process of McBSPs
        1. 34.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 34.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 34.3.2 Companding (Compressing and Expanding) Data
        1. 34.3.2.1 Companding Formats
        2. 34.3.2.2 Capability to Compand Internal Data
        3. 34.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 34.3.3 Clocking and Framing Data
        1. 34.3.3.1 Clocking
        2. 34.3.3.2 Serial Words
        3. 34.3.3.3 Frames and Frame Synchronization
        4. 34.3.3.4 Generating Transmit and Receive Interrupts
          1. 34.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 34.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 34.3.3.6 Frame Frequency
        7. 34.3.3.7 Maximum Frame Frequency
      4. 34.3.4 Frame Phases
        1. 34.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 34.3.4.2 Single-Phase Frame Example
        3. 34.3.4.3 Dual-Phase Frame Example
        4. 34.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 34.3.5 McBSP Reception
      6. 34.3.6 McBSP Transmission
      7. 34.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 34.4  McBSP Sample Rate Generator
      1. 34.4.1 Block Diagram
        1. 34.4.1.1 Clock Generation in the Sample Rate Generator
        2. 34.4.1.2 Choosing an Input Clock
        3. 34.4.1.3 Choosing a Polarity for the Input Clock
        4. 34.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 34.4.1.4.1 CLKG Frequency
        5. 34.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 34.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 34.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 34.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 34.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 34.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 34.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 34.4.3.2 Synchronization Examples
      4. 34.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 34.5  McBSP Exception/Error Conditions
      1. 34.5.1 Types of Errors
      2. 34.5.2 Overrun in the Receiver
        1. 34.5.2.1 Example of Overrun Condition
        2. 34.5.2.2 Example of Preventing Overrun Condition
      3. 34.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 34.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 34.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 34.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 34.5.4 Overwrite in the Transmitter
        1. 34.5.4.1 Example of Overwrite Condition
        2. 34.5.4.2 Preventing Overwrites
      5. 34.5.5 Underflow in the Transmitter
        1. 34.5.5.1 Example of the Underflow Condition
        2. 34.5.5.2 Example of Preventing Underflow Condition
      6. 34.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 34.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 34.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 34.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 34.6  Multichannel Selection Modes
      1. 34.6.1 Channels, Blocks, and Partitions
      2. 34.6.2 Multichannel Selection
      3. 34.6.3 Configuring a Frame for Multichannel Selection
      4. 34.6.4 Using Two Partitions
        1. 34.6.4.1 Assigning Blocks to Partitions A and B
        2. 34.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 34.6.5 Using Eight Partitions
      6. 34.6.6 Receive Multichannel Selection Mode
      7. 34.6.7 Transmit Multichannel Selection Modes
        1. 34.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 34.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 34.6.8 Using Interrupts Between Block Transfers
    7. 34.7  SPI Operation Using the Clock Stop Mode
      1. 34.7.1 SPI Protocol
      2. 34.7.2 Clock Stop Mode
      3. 34.7.3 Enable and Configure the Clock Stop Mode
      4. 34.7.4 Clock Stop Mode Timing Diagrams
      5. 34.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 34.7.6 McBSP as the SPI Master
      7. 34.7.7 McBSP as an SPI Slave
    8. 34.8  Receiver Configuration
      1. 34.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 34.8.2  Resetting and Enabling the Receiver
        1. 34.8.2.1 Reset Considerations
      3. 34.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 34.8.4  Digital Loopback Mode
      5. 34.8.5  Clock Stop Mode
      6. 34.8.6  Receive Multichannel Selection Mode
      7. 34.8.7  Receive Frame Phases
      8. 34.8.8  Receive Word Lengths
        1. 34.8.8.1 Word Length Bits
      9. 34.8.9  Receive Frame Length
        1. 34.8.9.1 Selected Frame Length
      10. 34.8.10 Receive Frame-Synchronization Ignore Function
        1. 34.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 34.8.10.2 Examples of Effects of RFIG
      11. 34.8.11 Receive Companding Mode
        1. 34.8.11.1 Companding
        2. 34.8.11.2 Format of Expanded Data
        3. 34.8.11.3 Companding Internal Data
        4. 34.8.11.4 Option to Receive LSB First
      12. 34.8.12 Receive Data Delay
        1. 34.8.12.1 Data Delay
        2. 34.8.12.2 0-Bit Data Delay
        3. 34.8.12.3 2-Bit Data Delay
      13. 34.8.13 Receive Sign-Extension and Justification Mode
        1. 34.8.13.1 Sign-Extension and the Justification
      14. 34.8.14 Receive Interrupt Mode
      15. 34.8.15 Receive Frame-Synchronization Mode
        1. 34.8.15.1 Receive Frame-Synchronization Modes
      16. 34.8.16 Receive Frame-Synchronization Polarity
        1. 34.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 34.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 34.8.17 Receive Clock Mode
        1. 34.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 34.8.18 Receive Clock Polarity
        1. 34.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 34.8.19 SRG Clock Divide-Down Value
        1. 34.8.19.1 Sample Rate Generator Clock Divider
      20. 34.8.20 SRG Clock Synchronization Mode
      21. 34.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 34.8.22 SRG Input Clock Polarity
        1. 34.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 34.9  Transmitter Configuration
      1. 34.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 34.9.2  Resetting and Enabling the Transmitter
        1. 34.9.2.1 Reset Considerations
      3. 34.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 34.9.4  Digital Loopback Mode
      5. 34.9.5  Clock Stop Mode
      6. 34.9.6  Transmit Multichannel Selection Mode
      7. 34.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 34.9.8  Transmit Frame Phases
      9. 34.9.9  Transmit Word Lengths
        1. 34.9.9.1 Word Length Bits
      10. 34.9.10 Transmit Frame Length
        1. 34.9.10.1 Selected Frame Length
      11. 34.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 34.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 34.9.11.2 Examples Showing the Effects of XFIG
      12. 34.9.12 Transmit Companding Mode
        1. 34.9.12.1 Companding
        2. 34.9.12.2 Format for Data To Be Compressed
        3. 34.9.12.3 Capability to Compand Internal Data
        4. 34.9.12.4 Option to Transmit LSB First
      13. 34.9.13 Transmit Data Delay
        1. 34.9.13.1 Data Delay
        2. 34.9.13.2 0-Bit Data Delay
        3. 34.9.13.3 2-Bit Data Delay
      14. 34.9.14 Transmit DXENA Mode
      15. 34.9.15 Transmit Interrupt Mode
      16. 34.9.16 Transmit Frame-Synchronization Mode
        1. 34.9.16.1 Other Considerations
      17. 34.9.17 Transmit Frame-Synchronization Polarity
        1. 34.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 34.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 34.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 34.9.19 Transmit Clock Mode
        1. 34.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 34.9.19.2 Other Considerations
      20. 34.9.20 Transmit Clock Polarity
        1. 34.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 34.10 Emulation and Reset Considerations
      1. 34.10.1 McBSP Emulation Mode
      2. 34.10.2 Resetting and Initializing McBSPs
        1. 34.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 34.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 34.10.2.3 McBSP Initialization Procedure
        4. 34.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 34.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 34.11 Data Packing Examples
      1. 34.11.1 Data Packing Using Frame Length and Word Length
      2. 34.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 34.12 Interrupt Generation
      1. 34.12.1 McBSP Receive Interrupt Generation
      2. 34.12.2 McBSP Transmit Interrupt Generation
      3. 34.12.3 Error Flags
    13. 34.13 McBSP Modes
    14. 34.14 Special Case: External Device is the Transmit Frame Master
    15. 34.15 Software
      1. 34.15.1 MCBSP Examples
        1. 34.15.1.1 Pin Setup for McBSP module
        2. 34.15.1.2 McBSP loopback example
        3. 34.15.1.3 McBSP loopback with DMA example.
        4. 34.15.1.4 McBSP loopback with interrupts example
        5. 34.15.1.5 McBSP loopback with interrupts example
        6. 34.15.1.6 McBSP loopback example using SPI mode
        7. 34.15.1.7 McBSP external loopback example
        8. 34.15.1.8 McBSP external loopback example using SPI mode
        9. 34.15.1.9 McBSP TDM-8 Test
    16. 34.16 McBSP Registers
      1. 34.16.1 MCBSP Base Address Table (C28)
      2. 34.16.2 McBSP_REGS Registers
      3. 34.16.3 MCBSP Registers to Driverlib Functions
  37. 35Power Management Bus Module (PMBus)
    1. 35.1 Introduction
      1. 35.1.1 PMBUS Related Collateral
      2. 35.1.2 Features
      3. 35.1.3 Block Diagram
    2. 35.2 Configuring Device Pins
    3. 35.3 Slave Mode Operation
      1. 35.3.1 Configuration
      2. 35.3.2 Message Handling
        1. 35.3.2.1  Quick Command
        2. 35.3.2.2  Send Byte
        3. 35.3.2.3  Receive Byte
        4. 35.3.2.4  Write Byte and Write Word
        5. 35.3.2.5  Read Byte and Read Word
        6. 35.3.2.6  Process Call
        7. 35.3.2.7  Block Write
        8. 35.3.2.8  Block Read
        9. 35.3.2.9  Block Write-Block Read Process Call
        10. 35.3.2.10 Alert Response
        11. 35.3.2.11 Extended Command
        12. 35.3.2.12 Group Command
    4. 35.4 Master Mode Operation
      1. 35.4.1 Configuration
      2. 35.4.2 Message Handling
        1. 35.4.2.1  Quick Command
        2. 35.4.2.2  Send Byte
        3. 35.4.2.3  Receive Byte
        4. 35.4.2.4  Write Byte and Write Word
        5. 35.4.2.5  Read Byte and Read Word
        6. 35.4.2.6  Process Call
        7. 35.4.2.7  Block Write
        8. 35.4.2.8  Block Read
        9. 35.4.2.9  Block Write-Block Read Process Call
        10. 35.4.2.10 Alert Response
        11. 35.4.2.11 Extended Command
        12. 35.4.2.12 Group Command
    5. 35.5 PMBus Registers
      1. 35.5.1 PMBUS Base Address Table (C28)
      2. 35.5.2 PMBUS_REGS Registers
      3. 35.5.3 PMBUS Registers to Driverlib Functions
  38. 36Serial Communications Interface (SCI)
    1. 36.1  Introduction
      1. 36.1.1 Features
      2. 36.1.2 SCI Related Collateral
      3. 36.1.3 Block Diagram
    2. 36.2  Architecture
    3. 36.3  SCI Module Signal Summary
    4. 36.4  Configuring Device Pins
    5. 36.5  Multiprocessor and Asynchronous Communication Modes
    6. 36.6  SCI Programmable Data Format
    7. 36.7  SCI Multiprocessor Communication
      1. 36.7.1 Recognizing the Address Byte
      2. 36.7.2 Controlling the SCI TX and RX Features
      3. 36.7.3 Receipt Sequence
    8. 36.8  Idle-Line Multiprocessor Mode
      1. 36.8.1 Idle-Line Mode Steps
      2. 36.8.2 Block Start Signal
      3. 36.8.3 Wake-Up Temporary (WUT) Flag
        1. 36.8.3.1 Sending a Block Start Signal
      4. 36.8.4 Receiver Operation
    9. 36.9  Address-Bit Multiprocessor Mode
      1. 36.9.1 Sending an Address
    10. 36.10 SCI Communication Format
      1. 36.10.1 Receiver Signals in Communication Modes
      2. 36.10.2 Transmitter Signals in Communication Modes
    11. 36.11 SCI Port Interrupts
      1. 36.11.1 Break Detect
    12. 36.12 SCI Baud Rate Calculations
    13. 36.13 SCI Enhanced Features
      1. 36.13.1 SCI FIFO Description
      2. 36.13.2 SCI Auto-Baud
      3. 36.13.3 Autobaud-Detect Sequence
    14. 36.14 Software
      1. 36.14.1 SCI Examples
        1. 36.14.1.1 Tune Baud Rate via UART Example
        2. 36.14.1.2 SCI FIFO Digital Loop Back
        3. 36.14.1.3 Watchdog Reset - C28X_DUAL
        4. 36.14.1.4 NMI handling - C28X_DUAL
        5. 36.14.1.5 SCI Digital Loop Back with Interrupts
        6. 36.14.1.6 SCI Echoback
        7. 36.14.1.7 stdout redirect example
    15. 36.15 SCI Registers
      1. 36.15.1 SCI Base Address Table (C28)
      2. 36.15.2 SCI_REGS Registers
      3. 36.15.3 SCI Registers to Driverlib Functions
  39. 37Serial Peripheral Interface (SPI)
    1. 37.1 Introduction
      1. 37.1.1 Features
      2. 37.1.2 SPI Related Collateral
      3. 37.1.3 Block Diagram
    2. 37.2 System-Level Integration
      1. 37.2.1 SPI Module Signals
      2. 37.2.2 Configuring Device Pins
        1. 37.2.2.1 GPIOs Required for High-Speed Mode
      3. 37.2.3 SPI Interrupts
      4. 37.2.4 DMA Support
    3. 37.3 SPI Operation
      1. 37.3.1  Introduction to Operation
      2. 37.3.2  Master Mode
      3. 37.3.3  Slave Mode
      4. 37.3.4  Data Format
        1. 37.3.4.1 Transmission of Bit from SPIRXBUF
      5. 37.3.5  Baud Rate Selection
        1. 37.3.5.1 Baud Rate Determination
        2. 37.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 37.3.6  SPI Clocking Schemes
      7. 37.3.7  SPI FIFO Description
      8. 37.3.8  SPI DMA Transfers
        1. 37.3.8.1 Transmitting Data Using SPI with DMA
        2. 37.3.8.2 Receiving Data Using SPI with DMA
      9. 37.3.9  SPI High-Speed Mode
      10. 37.3.10 SPI 3-Wire Mode Description
    4. 37.4 Programming Procedure
      1. 37.4.1 Initialization Upon Reset
      2. 37.4.2 Configuring the SPI
      3. 37.4.3 Configuring the SPI for High-Speed Mode
      4. 37.4.4 Data Transfer Example
      5. 37.4.5 SPI 3-Wire Mode Code Examples
        1. 37.4.5.1 3-Wire Master Mode Transmit
        2.       1924
          1. 37.4.5.2.1 3-Wire Master Mode Receive
        3.       1926
          1. 37.4.5.2.1 3-Wire Slave Mode Transmit
        4.       1928
          1. 37.4.5.2.1 3-Wire Slave Mode Receive
      6. 37.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 37.5 Software
      1. 37.5.1 SPI Examples
        1. 37.5.1.1 SPI Digital Loopback
        2. 37.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 37.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 37.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 37.5.1.5 SPI Digital Loopback with DMA
        6. 37.5.1.6 SPI EEPROM
        7. 37.5.1.7 SPI DMA EEPROM
    6. 37.6 SPI Registers
      1. 37.6.1 SPI Base Address Table (C28)
      2. 37.6.2 SPI_REGS Registers
      3. 37.6.3 SPI Registers to Driverlib Functions
  40. 38Universal Serial Bus (USB) Controller
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 USB Related Collateral
      3. 38.1.3 Block Diagram
        1. 38.1.3.1 Signal Description
        2. 38.1.3.2 VBus Recommendations
    2. 38.2 Functional Description
      1. 38.2.1 Operation as a Device
        1. 38.2.1.1 Control and Configurable Endpoints
          1. 38.2.1.1.1 IN Transactions as a Device
          2. 38.2.1.1.2 Out Transactions as a Device
          3. 38.2.1.1.3 Scheduling
          4. 38.2.1.1.4 Additional Actions
          5. 38.2.1.1.5 Device Mode Suspend
          6. 38.2.1.1.6 Start of Frame
          7. 38.2.1.1.7 USB Reset
          8. 38.2.1.1.8 Connect/Disconnect
      2. 38.2.2 Operation as a Host
        1. 38.2.2.1 Endpoint Registers
        2. 38.2.2.2 IN Transactions as a Host
        3. 38.2.2.3 OUT Transactions as a Host
        4. 38.2.2.4 Transaction Scheduling
        5. 38.2.2.5 USB Hubs
        6. 38.2.2.6 Babble
        7. 38.2.2.7 Host SUSPEND
        8. 38.2.2.8 USB RESET
        9. 38.2.2.9 Connect/Disconnect
      3. 38.2.3 DMA Operation
      4. 38.2.4 Address/Data Bus Bridge
    3. 38.3 Initialization and Configuration
      1. 38.3.1 Pin Configuration
      2. 38.3.2 Endpoint Configuration
    4. 38.4 USB Global Interrupts
    5. 38.5 Software
      1. 38.5.1 USB Examples
        1. 38.5.1.1  Wrapper for interrupt functions and USB support pins. - CM
        2. 38.5.1.2  USB CDC serial example
        3. 38.5.1.3  USB Composite Serial Device (usb_dev_cserial) - CM
        4. 38.5.1.4  USB HID Mouse Device
        5. 38.5.1.5  USB HID Mouse Device - CM
        6. 38.5.1.6  Data structures defining the USB mouse device. - CM
        7. 38.5.1.7  USB Device Keyboard
        8. 38.5.1.8  USB HID Keyboard Device (usb_dev_keyboard) - CM
        9. 38.5.1.9  Data structures defining the USB keyboard device. - CM
        10. 38.5.1.10 Data structures defining this bulk USB device. - CM
        11. 38.5.1.11 USB Generic Bulk Device (usb_dev_bulk) - CM
        12. 38.5.1.12 USB Generic Bulk Device
        13. 38.5.1.13 USB HID Mouse Host
        14. 38.5.1.14 USB HID Mouse Host (usb_host_mouse) - CM
        15. 38.5.1.15 USB HID Keyboard Host (usb_host_keyboard) - CM
        16. 38.5.1.16 USB HID Keyboard Host
        17. 38.5.1.17 USB Mass Storage Class Host
        18. 38.5.1.18 USB Mass Storage Class Host (usb_host_msc) - CM
        19. 38.5.1.19 USB Dual Detect
        20. 38.5.1.20 Data structures defining this bulk USB device. - CM
        21. 38.5.1.21 USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk) - CM
        22. 38.5.1.22 USB HUB Host example - CM
        23. 38.5.1.23 USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        24. 38.5.1.24 USB HUB Host example
    6. 38.6 USB Registers
      1. 38.6.1 USB Base Address Table (C28)
      2. 38.6.2 USB_REGS Registers
      3. 38.6.3 USB Registers to Driverlib Functions
  41. 39â–º CONNECTIVITY MANAGER (CM)
    1. 39.1 Technical Reference Manual Overview
  42. 40Connectivity Manager Subsystem
    1. 40.1 Connectivity Manager Overview
    2. 40.2 Connectivity Manager Functional Block Diagram
    3. 40.3 Arm® Cortex®-M4 Processor Core Overview
  43. 41Connectivity Manager System Control and Interrupts
    1. 41.1  Introduction
    2. 41.2  Reset
      1. 41.2.1 CPU1 SYSRS
      2. 41.2.2 System Reset Request (CMSYSRESETREQ)
      3. 41.2.3 CM NMI Watchdog Reset (CMNMIWDRSTn)
      4. 41.2.4 CM Secure Code Copy Reset (CMSCCRESETn)
    3. 41.3  CM Clocking
      1. 41.3.1 CM Clock Sources
      2. 41.3.2 CM Derived Clocks
      3. 41.3.3 CM Device Clock Domains
        1. 41.3.3.1 Connectivity Manager Clock (CMCLK)
        2. 41.3.3.2 CM Peripheral Subsystem Clock (CM.PERx.SYSCLK)
        3. 41.3.3.3 MCAN Bit Clock
      4. 41.3.4 CM Clock Connectivity
    4. 41.4  SysTick
    5. 41.5  Watchdog Timer
    6. 41.6  Exceptions and NMI
      1. 41.6.1 CM Subsystem Nested Vectored Interrupt Controller
      2. 41.6.2 CM Subsystem Exceptions Handling
      3. 41.6.3 CM Subsystem Non-Maskable Interrupt (CMNMI) Module
        1. 41.6.3.1 CM Subsystem NMI Sources
          1. 41.6.3.1.1 RAM/ROM Uncorrectable Error
          2. 41.6.3.1.2 Reset Request from EtherCAT
          3. 41.6.3.1.3 Clock Fail Condition
          4. 41.6.3.1.4 MCAN Uncorrectable Error
          5. 41.6.3.1.5 CM Windowed Watchdog Timed Out
          6. 41.6.3.1.6 Flash Uncorrectable Error
        2. 41.6.3.2 CM Subsystem NMIWD Module
          1. 41.6.3.2.1 Emulation Considerations
        3. 41.6.3.3 Handling of CMNMI
      4. 41.6.4 CM Interrupts/NMI to CPU1/CPU2
    7. 41.7  Nested Vectored Interrupt Controller (NVIC)
      1. 41.7.1 Level-Sensitive and Pulse Interrupts
      2. 41.7.2 Hardware and Software Control of Interrupts
      3. 41.7.3 NVIC Registers Access
    8. 41.8  32-Bit CM CPU Timers 0/1/2
    9. 41.9  Memory Controller Module
      1. 41.9.1 Functional Description
        1. 41.9.1.1 Dedicated RAM
        2. 41.9.1.2 Shared RAM
        3. 41.9.1.3 MSG RAM
        4. 41.9.1.4 ROM
        5. 41.9.1.5 Interleaving
        6. 41.9.1.6 Access Arbitration
        7. 41.9.1.7 Access Protection
        8. 41.9.1.8 Memory Error Detection, Correction and Error Handling
          1. 41.9.1.8.1 Error Detection and Correction
          2. 41.9.1.8.2 Error Handling
          3. 41.9.1.8.3 Application Test Hooks for Error Detection and Correction
          4. 41.9.1.8.4 ROM Test
        9. 41.9.1.9 RAM Initialization
    10. 41.10 Memory Protection Unit (MPU)
      1. 41.10.1 Functional Description
      2. 41.10.2 Overlapping Regions
      3. 41.10.3 Sub-Regions
      4. 41.10.4 Programmers Model
    11. 41.11 Debug and Trace
      1. 41.11.1 Trace Port Interface Unit
    12. 41.12 CM-SysCtrl Registers
      1. 41.12.1  CM System Control Base Addresses
      2. 41.12.2  CM_MEMCFG_REGS Registers
      3. 41.12.3  CM_MEMORYDIAGERROR_REGS Registers
      4. 41.12.4  CM_MEMORYERROR_REGS Registers
      5. 41.12.5  CMSYSCTL_REGS Registers
      6. 41.12.6  CM_CPUTIMER_REGS Registers
      7. 41.12.7  MPU_REGS Registers
      8. 41.12.8  CM_NMI_INTRUPT_REGS Registers
      9. 41.12.9  NVIC Registers
      10. 41.12.10 SCB Registers
      11. 41.12.11 CSFR Registers
      12. 41.12.12 SYSTICK Registers
      13. 41.12.13 MPU Registers
      14. 41.12.14 CM_WD_REGS Registers
  44. 42Advanced Encryption Standard (AES) Accelerator
    1. 42.1 Introduction
      1. 42.1.1 AES Block Diagram
        1. 42.1.1.1 Interfaces
        2. 42.1.1.2 AES Subsystem
        3. 42.1.1.3 AES Wide-Bus Engine
      2. 42.1.2 AES Algorithm
    2. 42.2 AES Operating Modes
      1. 42.2.1  GCM Operation
      2. 42.2.2  CCM Operation
      3. 42.2.3  XTS Operation
      4. 42.2.4  ECB Feedback Mode
      5. 42.2.5  CBC Feedback Mode
      6. 42.2.6  CTR and ICM Feedback Modes
      7. 42.2.7  CFB Mode
      8. 42.2.8  F8 Mode
      9. 42.2.9  F9 Operation
      10. 42.2.10 CBC-MAC Operation
    3. 42.3 Extended and Combined Modes of Operations
      1. 42.3.1 GCM Protocol Operation
      2. 42.3.2 CCM Protocol Operation
      3. 42.3.3 Hardware Requests
    4. 42.4 AES Module Programming Guide
      1. 42.4.1 AES Low-Level Programming Models
        1. 42.4.1.1 Global Initialization
        2. 42.4.1.2 AES Operating Modes Configuration
        3. 42.4.1.3 AES Mode Configurations
        4. 42.4.1.4 AES Events Servicing
    5. 42.5 Software
      1. 42.5.1 AES Examples
        1. 42.5.1.1 AES ECB Encryption Example (CM) - CM
        2. 42.5.1.2 AES ECB De-cryption Example (CM) - CM
        3. 42.5.1.3 AES GCM Encryption Example (CM) - CM
        4. 42.5.1.4 AES GCM Decryption Example (CM) - CM
    6. 42.6 AES Registers
      1. 42.6.1 AES Base Addresses
      2. 42.6.2 AES_SS_REGS Registers
      3. 42.6.3 AES_REGS Registers
  45. 43Ethernet Media Access Controller (EMAC)
    1. 43.1 Introduction
      1. 43.1.1 Standard Compliance
      2. 43.1.2 MAC Features
        1. 43.1.2.1 MAC Tx and Rx Features
        2. 43.1.2.2 MAC Tx Features
        3. 43.1.2.3 MAC Rx Features
    2. 43.2 System Level Integration
      1. 43.2.1 Ethernet Signal Connection and Description
        1. 43.2.1.1 MII Interface Signals
        2. 43.2.1.2 RMII Interface Signals
        3. 43.2.1.3 RevMII Interface Signals
        4. 43.2.1.4 Pulse Per Second Signals
      2. 43.2.2 Configuring Device Pins
      3. 43.2.3 MAC Interface Selection
      4. 43.2.4 Clocks for Ethernet Module
      5. 43.2.5 RMII Mode Clocking
      6. 43.2.6 RevMII Mode Clocking
      7. 43.2.7 Configuring Trigger Sources for Time Stamping
        1. 43.2.7.1 Software Trigger for Time Stamping
      8. 43.2.8 Ethernet Interrupts
    3. 43.3 Features
      1. 43.3.1 Multiple Channels and Queues Support
        1. 43.3.1.1 Multiple Queues and Channels in Transmit Path
        2. 43.3.1.2 Multiple Queues and Channels in Receive Path
        3. 43.3.1.3 Rx Queue to DMA Mapping
        4. 43.3.1.4 Selection of Tag Priorities Assigned to Tx and Rx Queues
        5. 43.3.1.5 Rx Side Routing from MAC to Queues
      2. 43.3.2 IEEE 1588 Timestamp Support
        1. 43.3.2.1 Feature Description
          1. 43.3.2.1.1 Clock Types
            1. 43.3.2.1.1.1 Peer-to-Peer Transparent Clock (P2PTC) Message Support
            2. 43.3.2.1.1.2 Timestamp Correction
            3. 43.3.2.1.1.3 Ingress Correction
            4. 43.3.2.1.1.4 Egress Correction
            5. 43.3.2.1.1.5 Frequency Range of Reference Timing Clock
          2. 43.3.2.1.2 Maximum PTP Clock Frequency
          3. 43.3.2.1.3 Minimum PTP Clock Frequency
          4. 43.3.2.1.4 PTP Processing and Control
          5. 43.3.2.1.5 PTP Packets Over IPv4
          6. 43.3.2.1.6 PTP Frames Over IPv6
          7. 43.3.2.1.7 PTP Packets Over Ethernet
          8. 43.3.2.1.8 Transmit Path Functions
          9. 43.3.2.1.9 Receive Path Functions
        2. 43.3.2.2 IEEE 1588 System Time Source
          1. 43.3.2.2.1 External Timestamp Input
          2. 43.3.2.2.2 Internal Reference Time
          3. 43.3.2.2.3 System Time Register Module
        3. 43.3.2.3 IEEE 1588 Higher Word Register
        4. 43.3.2.4 IEEE 1588 Auxillary Snapshot
        5. 43.3.2.5 Flexible Pulse-Per-Second Output
          1. 43.3.2.5.1 PPS Start or Stop Time
          2. 43.3.2.5.2 PPS Width and Interval
      3. 43.3.3 Packet Filtering
        1. 43.3.3.1 Packet Filtering Sequence
        2. 43.3.3.2 Destination Address Filtering
        3. 43.3.3.3 Source Address Filtering
        4. 43.3.3.4 Inverse Filtering
        5. 43.3.3.5 VLAN Filtering
          1. 43.3.3.5.1 Comparison Modes
          2. 43.3.3.5.2 Filter Status
          3. 43.3.3.5.3 Stripping
        6. 43.3.3.6 Layer 3 and Layer 4 Filtering
          1. 43.3.3.6.1 Layer 3 Filtering
      4. 43.3.4 VLAN Support
        1. 43.3.4.1 Double VLAN Processing
          1. 43.3.4.1.1 Transmit Path
          2. 43.3.4.1.2 Receive Path
        2. 43.3.4.2 Double VLAN-Related Registers
        3. 43.3.4.3 Source Address and VLAN Insertion, Replacement, or Deletion
          1. 43.3.4.3.1 Programming VLAN Insertion, Replacement, or Deletion
        4. 43.3.4.4 Queue/Channel Based VLAN Tag Insertion on Tx
      5. 43.3.5 TCP/IP Offloading Features
        1. 43.3.5.1 Transmit Checksum Offload Engine
          1. 43.3.5.1.1 IP Header Checksum Engine
          2. 43.3.5.1.2 TCP/UDP/ICMP Checksum Engine
        2. 43.3.5.2 Receive Checksum Offload Engine
        3. 43.3.5.3 TCP/IP Segmentation Offload (TSO) Engine
          1. 43.3.5.3.1 DMA Operation with TSO Feature
            1. 43.3.5.3.1.1 TCP/IP Header Fields
            2. 43.3.5.3.1.2 Header and Payload Fields of Segmented Packets
        4. 43.3.5.4 Segmentation Versus Fragmentation
        5. 43.3.5.5 Using the IPv4 ARP Offload Engine
        6. 43.3.5.6 Energy Efficient Ethernet (EEE) Support
          1. 43.3.5.6.1 Magic Packet
          2. 43.3.5.6.2 Remote Wakeup Filter
          3. 43.3.5.6.3 Energy Efficient Ethernet (EEE)
            1. 43.3.5.6.3.1 Transmit Path Functions
          4. 43.3.5.6.4 Automated Entry/Exit of LPI mode in Transmit Path
          5. 43.3.5.6.5 Receive Path Functions
        7. 43.3.5.7 Automated Entry/Exit of LPI Mode in Transmit Path
        8. 43.3.5.8 Receive Path Functions
      6. 43.3.6 Loopback Mode
      7. 43.3.7 Reverse Media Independent Interface (RevMII)
        1. 43.3.7.1 RevMII Register Maps
        2. 43.3.7.2 MAC_RevMII_PHY_Control
        3. 43.3.7.3 MAC_RevMII_Common_Status
        4. 43.3.7.4 MAC_RevMII_Common_Ext_Status
        5. 43.3.7.5 MAC_RevMII_Interrupt_Status_Mask
        6. 43.3.7.6 MAC_RevMII_Remote_PHY_Status
        7. 43.3.7.7 MAC_RevMII_PHY_Status Register
    4. 43.4 Descriptors
      1. 43.4.1 Descriptor Structure
      2. 43.4.2 Transmit Descriptor
        1. 43.4.2.1 Transmit Normal Descriptor (Read Format)
          1. 43.4.2.1.1 TDES0 Normal Descriptor (Read Format)
          2. 43.4.2.1.2 TDES1 Normal Descriptor (Read Format)
          3. 43.4.2.1.3 TDES2 Normal Descriptor (Read Format)
          4. 43.4.2.1.4 TDES3 Normal Descriptor (Read Format)
        2. 43.4.2.2 Transmit Normal Descriptor (Write-Back Format)
          1. 43.4.2.2.1 TDES0 Normal Descriptor (Write-Back Format)
          2. 43.4.2.2.2 TDES1 Normal Descriptor (Write-Back Format)
          3. 43.4.2.2.3 TDES2 Normal Descriptor (Write-Back Format)
          4. 43.4.2.2.4 TDES3 Normal Descriptor (Write-Back Format)
        3. 43.4.2.3 Transmit Context Descriptor
          1. 43.4.2.3.1 TDES0 Context Descriptor
          2. 43.4.2.3.2 TDES1 Context Descriptor
          3. 43.4.2.3.3 TDES2 Context Descriptor
          4. 43.4.2.3.4 TDES3 Context Descriptor
      3. 43.4.3 Receive Descriptor
        1. 43.4.3.1 Receive Normal Descriptor (Read Format)
          1. 43.4.3.1.1 RDES0 Normal Descriptor (Read Format)
          2. 43.4.3.1.2 RDES1 Normal Descriptor (Read Format)
          3. 43.4.3.1.3 RDES2 Normal Descriptor (Read Format)
          4. 43.4.3.1.4 RDES3 Normal Descriptor (Read Format)
        2. 43.4.3.2 Receive Normal Descriptor (Write-Back Format)
          1. 43.4.3.2.1 RDES0 Normal Descriptor (Write-Back Format)
          2. 43.4.3.2.2 RDES1 Normal Descriptor (Write-Back Format)
          3. 43.4.3.2.3 RDES2 Normal Descriptor (Write-Back Format)
          4. 43.4.3.2.4 RDES3 Normal Descriptor (Write-Back Format)
        3. 43.4.3.3 Receive Context Descriptor
          1. 43.4.3.3.1 RDES0 Context Descriptor
          2. 43.4.3.3.2 RDES1 Context Descriptor
          3. 43.4.3.3.3 RDES2 Context Descriptor
          4. 43.4.3.3.4 RDES3 Context Descriptor
    5. 43.5 Programming
      1. 43.5.1 Initializing DMA
      2. 43.5.2 Initializing MTL Registers
      3. 43.5.3 Initializing MAC
      4. 43.5.4 Performing Normal Receive and Transmit Operation
      5. 43.5.5 Stopping and Starting Transmission
      6. 43.5.6 Programming Guidelines for Multi-Channel Multi-Queuing
        1. 43.5.6.1 Transmit
        2. 43.5.6.2 Receive
        3. 43.5.6.3 Programming Guidelines for Recovering from DMA Channel Failure
          1. 43.5.6.3.1 Recovering from the Receive DMA Channel Failure
          2. 43.5.6.3.2 Recovering from the Transmit DMA Channel Failure
        4. 43.5.6.4 Programming Guidelines for IEEE 1588 Timestamping
          1. 43.5.6.4.1 Initialization Guidelines for System Time Generation
          2. 43.5.6.4.2 System Time Correction
            1. 43.5.6.4.2.1 Coarse Correction Method
            2. 43.5.6.4.2.2 Fine Correction Method
        5. 43.5.6.5 Programming Guidelines for Energy Efficient Ethernet
          1. 43.5.6.5.1 Entering and Exiting the Tx LPI Mode
          2. 43.5.6.5.2 Gating Off the CSR Clock in the LPI Mode
          3. 43.5.6.5.3 Rx LPI Mode
          4. 43.5.6.5.4 Gating Off the CSR Clock in the Tx LPI Mode
        6. 43.5.6.6 Programming Guidelines for Flexible Pulse-Per-Second Output
          1. 43.5.6.6.1 Generating Single Pulse on PPS
          2. 43.5.6.6.2 Generating Next Pulse on PPS
          3. 43.5.6.6.3 Generating a Pulse Train on PPS
          4. 43.5.6.6.4 Generating an Interrupt without Affecting the PPS
        7. 43.5.6.7 Programming Guidelines for TSO
    6. 43.6 Software
      1. 43.6.1 ETHERNET Examples
        1. 43.6.1.1  Ethernet + IPC basic message passing example with interrupt - C28X_CM
        2. 43.6.1.2  Ethernet + IPC basic message passing example with interrupt - C28X_CM
        3. 43.6.1.3  Ethernet MAC Internal Loopback - CM
        4. 43.6.1.4  Ethernet Basic Transmit and Receive PHY Loopback - CM
        5. 43.6.1.5  Ethernet Threshold mode with level PHY loopback - CM
        6. 43.6.1.6  Ethernet PTP Basic Master - CM
        7. 43.6.1.7  Ethernet PTP Basic Slave - CM
        8. 43.6.1.8  Ethernet PTP Offload Master - CM
        9. 43.6.1.9  Ethernet PTP Offload Slave - CM
        10. 43.6.1.10 Ethernet MAC CRC and Checksum Offload - CM
        11. 43.6.1.11 Ethernet Transmit Segmentation Offload - CM
        12. 43.6.1.12 Ethernet MAC Internal Loopback - CM
        13. 43.6.1.13 Ethernet RevMII Example MII side - CM
        14. 43.6.1.14 Ethernet RevMII Example RevMII side - CM
        15. 43.6.1.15 Ethernet Low Latency Interrupt - CM
    7. 43.7 Ethernet Registers
      1. 43.7.1 Ethernet Base Addresses
      2. 43.7.2 ETHERNETSS_REGS Registers
      3. 43.7.3 EMAC_REGS Registers
  46. 44Generic Cyclic Redundancy Check (GCRC)
    1. 44.1 Generic CRC Overview
      1. 44.1.1 GCRC Features
      2. 44.1.2 GCRC Block Diagram
    2. 44.2 GCRC Functional Description
      1. 44.2.1 GCRC Polynomials
      2. 44.2.2 Fixed Polynomial
      3. 44.2.3 GCRC Data Input
      4. 44.2.4 GCRC Execution Sequence Flow
      5. 44.2.5 GCRC Transformations
        1. 44.2.5.1 Endianness Transformation
        2. 44.2.5.2 Mask Transformation
        3. 44.2.5.3 Bit Reversal Transformation
    3. 44.3 Software
      1. 44.3.1 GCRC Examples
        1. 44.3.1.1 GCRC example - CM
    4. 44.4 GCRC Registers
      1. 44.4.1 GCRC Base Addresses
      2. 44.4.2 GCRC_REGS Registers
  47. 45Modular Controller Area Network (MCAN)
    1. 45.1 MCAN Introduction
      1. 45.1.1 MCAN Related Collateral
      2. 45.1.2 MCAN Features
    2. 45.2 MCAN Environment
    3. 45.3 CAN Network Basics
    4. 45.4 MCAN Integration
    5. 45.5 MCAN Functional Description
      1. 45.5.1  Module Clocking Requirements
      2. 45.5.2  Interrupt Requests
      3. 45.5.3  Operating Modes
        1. 45.5.3.1 Software Initialization
        2. 45.5.3.2 Normal Operation
        3. 45.5.3.3 CAN FD Operation
      4. 45.5.4  Transmitter Delay Compensation
        1. 45.5.4.1 Description
        2. 45.5.4.2 Transmitter Delay Compensation Measurement
      5. 45.5.5  Restricted Operation Mode
      6. 45.5.6  Bus Monitoring Mode
      7. 45.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 45.5.7.1 Frame Transmission in DAR Mode
      8. 45.5.8  Clock Stop Mode
        1. 45.5.8.1 Suspend Mode
        2. 45.5.8.2 Wakeup Request
      9. 45.5.9  Test Modes
        1. 45.5.9.1 External Loop Back Mode
        2. 45.5.9.2 Internal Loop Back Mode
      10. 45.5.10 Timestamp Generation
        1. 45.5.10.1 External Timestamp Counter
      11. 45.5.11 Timeout Counter
      12. 45.5.12 Safety
        1. 45.5.12.1 ECC Wrapper
        2. 45.5.12.2 ECC Aggregator
          1. 45.5.12.2.1 ECC Aggregator Overview
          2. 45.5.12.2.2 ECC Aggregator Registers
        3. 45.5.12.3 Reads to ECC Control and Status Registers
        4. 45.5.12.4 ECC Interrupts
      13. 45.5.13 Rx Handling
        1. 45.5.13.1 Acceptance Filtering
          1. 45.5.13.1.1 Range Filter
          2. 45.5.13.1.2 Filter for Specific IDs
          3. 45.5.13.1.3 Classic Bit Mask Filter
          4. 45.5.13.1.4 Standard Message ID Filtering
          5. 45.5.13.1.5 Extended Message ID Filtering
        2. 45.5.13.2 Rx FIFOs
          1. 45.5.13.2.1 Rx FIFO Blocking Mode
          2. 45.5.13.2.2 Rx FIFO Overwrite Mode
        3. 45.5.13.3 Dedicated Rx Buffers
          1. 45.5.13.3.1 Rx Buffer Handling
      14. 45.5.14 Tx Handling
        1. 45.5.14.1 Transmit Pause
        2. 45.5.14.2 Dedicated Tx Buffers
        3. 45.5.14.3 Tx FIFO
        4. 45.5.14.4 Tx Queue
        5. 45.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 45.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 45.5.14.7 Transmit Cancellation
        8. 45.5.14.8 Tx Event Handling
      15. 45.5.15 FIFO Acknowledge Handling
      16. 45.5.16 Message RAM
        1. 45.5.16.1 Message RAM Configuration
        2. 45.5.16.2 Rx Buffer and FIFO Element
        3. 45.5.16.3 Tx Buffer Element
        4. 45.5.16.4 Tx Event FIFO Element
        5. 45.5.16.5 Standard Message ID Filter Element
        6. 45.5.16.6 Extended Message ID Filter Element
    6. 45.6 Software
      1. 45.6.1 MCAN Examples
        1. 45.6.1.1  MCAN Internal Loopback with Interrupt - CM
        2. 45.6.1.2  MCAN Internal Loopback with Interrupt
        3. 45.6.1.3  MCAN External Loopback with Interrupt - CM
        4. 45.6.1.4  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        5. 45.6.1.5  MCAN receive using Rx Buffer
        6. 45.6.1.6  MCAN External Reception (with mask filter) into RX-FIFO1
        7. 45.6.1.7  MCAN Classic frames transmission using Tx Buffer
        8. 45.6.1.8  MCAN External Reception (with RANGE filter) into RX-FIFO1
        9. 45.6.1.9  MCAN External Transmit using Tx Buffer
        10. 45.6.1.10 MCAN receive using Rx Buffer
        11. 45.6.1.11 MCAN Internal Loopback with Interrupt
        12. 45.6.1.12 MCAN External Transmit using Tx Buffer
    7. 45.7 MCAN Registers
      1. 45.7.1 MCAN Base Address Table (C28)
      2. 45.7.2 CM MCAN Base Address Table (CM)
      3. 45.7.3 MCANSS_REGS Registers
      4. 45.7.4 MCAN_REGS Registers
      5. 45.7.5 MCAN_ERROR_REGS Registers
  48. 46Connectivity Manager Inter-Integrated Circuit (I2C) Module
    1. 46.1 Introduction
      1. 46.1.1 Features
      2. 46.1.2 Block Diagram
    2. 46.2 Functional Description
      1. 46.2.1 I2C Bus Functional Overview
        1. 46.2.1.1  START and STOP Conditions
        2. 46.2.1.2  Data Format With 7-Bit Address
        3. 46.2.1.3  Data Validity
        4. 46.2.1.4  Acknowledge
        5. 46.2.1.5  Repeated START
          1. 46.2.1.5.1 Repeated Start for Master Transmit
          2. 46.2.1.5.2 Repeated Start for Master Receive
        6. 46.2.1.6  Clock Low Time-out (CLTO)
        7. 46.2.1.7  Dual Address
        8. 46.2.1.8  Arbitration
        9. 46.2.1.9  Glitch Suppression in Multi-Master Configuration
        10. 46.2.1.10 SMBus Operation
          1. 46.2.1.10.1 Quick Command
      2. 46.2.2 Available Speed Modes
        1. 46.2.2.1 Standard, Fast, and Fast Plus Modes
        2. 46.2.2.2 High-Speed Mode
      3. 46.2.3 Interrupts
      4. 46.2.4 Loopback Operation
      5. 46.2.5 FIFO and µDMA Operation
        1. 46.2.5.1 Master Module Burst Mode
          1. 46.2.5.1.1 Master Module µDMA Functionality
        2. 46.2.5.2 Slave Module
      6. 46.2.6 Command Sequence Flow Charts
        1. 46.2.6.1 I2C Master Command Sequences
        2. 46.2.6.2 I2C Slave Command Sequences
    3. 46.3 Initialization and Configuration
      1. 46.3.1 Configure the I2C Module to Transmit a Single Byte as a Master
      2. 46.3.2 Configure the I2C Master to High-Speed Mode
    4. 46.4 CM I2C Registers
      1. 46.4.1 CM I2C Base Addresses
      2. 46.4.2 CM_I2C_REGS Registers
      3. 46.4.3 CM_I2C_WRITE_REGS Registers
  49. 47Synchronous Serial Interface (SSI)
    1. 47.1 Introduction
      1. 47.1.1 Features
      2. 47.1.2 Block Diagram
    2. 47.2 Functional Description
      1. 47.2.1 Bit Rate Generation
      2. 47.2.2 FIFO Operation
        1. 47.2.2.1 Transmit FIFO
        2. 47.2.2.2 Receive FIFO
      3. 47.2.3 SSInFSS Function
      4. 47.2.4 Interrupts
      5. 47.2.5 Frame Formats
        1. 47.2.5.1 Freescale SPI Frame Format
          1. 47.2.5.1.1 SPO Clock Polarity Bit
          2. 47.2.5.1.2 SPH Phase Control Bit
        2. 47.2.5.2 Freescale SPI Frame Format with SPO=0 and SPH=0
        3. 47.2.5.3 Freescale SPI Frame Format with SPO=0 and SPH=1
        4. 47.2.5.4 Freescale SPI Frame Format with SPO=1 and SPH=0
        5. 47.2.5.5 Freescale SPI Frame Format with SPO=1 and SPH=1
      6. 47.2.6 DMA Operation
    3. 47.3 Initialization and Configuration
    4. 47.4 Software
      1. 47.4.1 SSI Examples
        1. 47.4.1.1 SSI Loopback example with interrupts - CM
        2. 47.4.1.2 SSI Loopback example with UDMA - CM
    5. 47.5 SSI Registers
      1. 47.5.1 SSI Base Addresses
      2. 47.5.2 SSI_REGS Registers
  50. 48Universal Asynchronous Receiver/Transmitter (UART)
    1. 48.1 Introduction
      1. 48.1.1 Features
      2. 48.1.2 Block Diagram
    2. 48.2 Functional Description
      1. 48.2.1 Transmit and Receive Logic
      2. 48.2.2 Baud-Rate Generation
      3. 48.2.3 Data Transmission
      4. 48.2.4 Serial IR (SIR)
      5. 48.2.5 9-Bit UART Mode
      6. 48.2.6 FIFO Operation
      7. 48.2.7 Interrupts
      8. 48.2.8 Loopback Operation
      9. 48.2.9 DMA Operation
    3. 48.3 Initialization and Configuration
    4. 48.4 Software
      1. 48.4.1 UART Examples
        1. 48.4.1.1 UART Echoback - CM
        2. 48.4.1.2 UART Loopback example with UDMA - CM
    5. 48.5 UART Registers
      1. 48.5.1 UART Base Addresses
      2. 48.5.2 UART_REGS Registers
      3. 48.5.3 UART_REGS_WRITE Registers
  51. 49Micro Direct Memory Access (µDMA)
    1. 49.1 Introduction
      1. 49.1.1 Features
      2. 49.1.2 Block Diagram
    2. 49.2 Functional Description
      1. 49.2.1  Channel Assignments
      2. 49.2.2  Priority
      3. 49.2.3  Arbitration Size
      4. 49.2.4  Request Types
        1. 49.2.4.1 Single Request
        2. 49.2.4.2 Burst Request
      5. 49.2.5  Channel Configuration
      6. 49.2.6  Transfer Modes
        1. 49.2.6.1 Stop Mode
        2. 49.2.6.2 Basic Mode
        3. 49.2.6.3 Auto Mode
        4. 49.2.6.4 Ping-Pong
        5. 49.2.6.5 Memory Scatter-Gather
        6. 49.2.6.6 Peripheral Scatter-Gather
      7. 49.2.7  Transfer Size and Increment
      8. 49.2.8  Peripheral Interface
        1. 49.2.8.1 FIFO Peripherals
        2. 49.2.8.2 Trigger Peripherals
      9. 49.2.9  Software Request
      10. 49.2.10 Interrupts and Errors
    3. 49.3 Initialization and Configuration
      1. 49.3.1 Module Initialization
      2. 49.3.2 Configuring a Memory-to-Memory Transfer
        1. 49.3.2.1 Configure the Channel Attributes
        2. 49.3.2.2 Configure the Channel Control Structure
          1. 49.3.2.2.1 Configure the Source and Destination
          2. 49.3.2.2.2 Configure Peripheral Interrupts
        3. 49.3.2.3 Start the Transfer
      3. 49.3.3 Configuring a Peripheral for Simple Transmit
        1. 49.3.3.1 Configure the Channel Attributes
        2. 49.3.3.2 Configure the Channel Control Structure
          1. 49.3.3.2.1 Configure the Source and Destination
        3. 49.3.3.3 Start the Transfer
      4. 49.3.4 Configuring a Peripheral for Ping-Pong Receive
        1. 49.3.4.1 Configure the Channel Attributes
        2. 49.3.4.2 Configure the Channel Control Structure
          1. 49.3.4.2.1 Configure the Source and Destination
        3. 49.3.4.3 Configure and Enable the Peripheral Interrupt
        4. 49.3.4.4 Process Interrupts
      5. 49.3.5 Configuring Channel Assignments
    4. 49.4 Software
      1. 49.4.1 UDMA Examples
        1. 49.4.1.1 uDMA RAM to RAM transfer - CM
        2. 49.4.1.2 uDMA RAM to RAM transfer - CM
    5. 49.5 µDMA Registers
      1. 49.5.1 µDMA Base Addresses
      2. 49.5.2 UDMAREGS Registers
      3. 49.5.3 UDMACHDES Registers
  52. 50Revision History

34.16.2 McBSP_REGS Registers

Table 34-77 lists the memory-mapped registers for the McBSP_REGS registers. All register offset addresses not listed in Table 34-77 should be considered as reserved locations and the register contents should not be modified.

Table 34-77 MCBSP_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hDRR2Data receive register bits 31-16Go
1hDRR1Data receive register bits 15-0Go
2hDXR2Data transmit register bits 31-16Go
3hDXR1Data transmit register bits 15-0Go
4hSPCR2Serial port control register 2Go
5hSPCR1Serial port control register 1Go
6hRCR2Receive Control register 2Go
7hRCR1Receive Control register 1Go
8hXCR2Transmit Control register 2Go
9hXCR1Transmit Control register 1Go
AhSRGR2Sample rate generator register 2Go
BhSRGR1Sample rate generator register 1Go
ChMCR2Multi-channel control register 2Go
DhMCR1Multi-channel control register 1Go
EhRCERAReceive channel enable partition AGo
FhRCERBReceive channel enable partition BGo
10hXCERATransmit channel enable partition AGo
11hXCERBTransmit channel enable partition BGo
12hPCRPin Control registerGo
13hRCERCReceive channel enable partition CGo
14hRCERDReceive channel enable partition DGo
15hXCERCTransmit channel enable partition CGo
16hXCERDTransmit channel enable partition DGo
17hRCEREReceive channel enable partition EGo
18hRCERFReceive channel enable partition FGo
19hXCERETransmit channel enable partition EGo
1AhXCERFTransmit channel enable partition FGo
1BhRCERGReceive channel enable partition GGo
1ChRCERHReceive channel enable partition HGo
1DhXCERGTransmit channel enable partition GGo
1EhXCERHTransmit channel enable partition HGo
23hMFFINTInterrupt enableGo

Complex bit access types are encoded to fit into small table cells. Table 34-78 shows the codes that are used for access types in this section.

Table 34-78 McBSP_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

34.16.2.1 DRR2 Register (Offset = 0h) [Reset = 0000h]

DRR2 is shown in Figure 34-67 and described in Table 34-79.

Return to the Summary Table.

DRR2 contains the upper 16 bits of the received data to be read by the CPU or DMA. DRR2 is only used if the word length is greater than 16 bits.

Figure 34-67 DRR2 Register
15141312111098
HWHB
R/W-0h
76543210
HWLB
R/W-0h
Table 34-79 DRR2 Register Field Descriptions
BitFieldTypeResetDescription
15-8HWHBR/W0hHigh word high byte

Reset type: SYSRSn

7-0HWLBR/W0hHigh word low byte

Reset type: SYSRSn

34.16.2.2 DRR1 Register (Offset = 1h) [Reset = 0000h]

DRR1 is shown in Figure 34-68 and described in Table 34-80.

Return to the Summary Table.

DRR1 contains the lower 16 bits of the received data to be read by either the CPU or DMA.

Figure 34-68 DRR1 Register
15141312111098
LWHB
R/W-0h
76543210
LWLB
R/W-0h
Table 34-80 DRR1 Register Field Descriptions
BitFieldTypeResetDescription
15-8LWHBR/W0hLow word high byte

Reset type: SYSRSn

7-0LWLBR/W0hLow word low byte

Reset type: SYSRSn

34.16.2.3 DXR2 Register (Offset = 2h) [Reset = 0000h]

DXR2 is shown in Figure 34-69 and described in Table 34-81.

Return to the Summary Table.

DXR2 contains the upper 16 bits of the data to be transmitted after being written by the CPU or DMA. DXR2 is only used if the word length is greater than 16 bits.

Figure 34-69 DXR2 Register
15141312111098
HWHB
R/W-0h
76543210
HWLB
R/W-0h
Table 34-81 DXR2 Register Field Descriptions
BitFieldTypeResetDescription
15-8HWHBR/W0hLow word high byte

Reset type: SYSRSn

7-0HWLBR/W0hLow word low byte

Reset type: SYSRSn

34.16.2.4 DXR1 Register (Offset = 3h) [Reset = 0000h]

DXR1 is shown in Figure 34-70 and described in Table 34-82.

Return to the Summary Table.

DXR1 contains the lower 16 bits of the data to be transmitted after being written by the CPU or DMA.

Figure 34-70 DXR1 Register
15141312111098
LWHB
R/W-0h
76543210
LWLB
R/W-0h
Table 34-82 DXR1 Register Field Descriptions
BitFieldTypeResetDescription
15-8LWHBR/W0hLow word high byte

Reset type: SYSRSn

7-0LWLBR/W0hLow word low byte

Reset type: SYSRSn

34.16.2.5 SPCR2 Register (Offset = 4h) [Reset = 0000h]

SPCR2 is shown in Figure 34-71 and described in Table 34-83.

Return to the Summary Table.

SPCR2 conatins control and status bits for various McBSP functions such as emulation modes, transmit interrupt mode control, transmitter status bits, and transmitter and other internal reset controls.

Figure 34-71 SPCR2 Register
15141312111098
RESERVEDFREESOFT
R-0hR/W-0hR/W-0h
76543210
FRSTGRSTXINTMXSYNCERRXEMPTYXRDYXRST
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR/W-0h
Table 34-83 SPCR2 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9FREER/W0hFree run bit.
When a breakpoint is encountered in the high-level language debugger, FREE determines whether the McBSP transmit and receive clocks continue to run or whether they are affected as determined by the SOFT bit. When one of the clocks stops, the corresponding data transfer (transmission or reception) stops.

Reset type: SYSRSn

8SOFTR/W0hSoft stop bit.
When FREE = 0, SOFT determines the response of the McBSP transmit and receive clocks when a breakpoint is encountered in the high-level language debugger. When one of the clocks stops, the corresponding data transfer (transmission or reception) stops.

Reset type: SYSRSn

7FRSTR/W0hFrame-synchronization logic reset bit.
The sample rate generator of the McBSP includes framesynchronization logic to generate an internal frame-synchronization signal. You can use FRST to take the frame-synchronization logic into and out of its reset state. This bit has a negative polarity
FRST = 0 indicates the reset state.

Reset type: SYSRSn


0h (R/W) = If you read a 0, the frame-synchronization logic is in its reset state.
If you write a 0, you reset the frame-synchronization logic.
In the reset state, the frame-synchronization logic does not generate a frame-synchronization signal
(FSG).
1h (R/W) = If you read a 1, the frame-synchronization logic is enabled.
If you write a 1, you enable the frame-synchronization logic by taking it out of its reset state.
When the frame-synchronization logic is enabled (FRST = 1) and the sample rate generator as a whole is enabled (GRST = 1), the frame-synchronization logic generates the frame-synchronization signal FSG as programmed.
6GRSTR/W0hSample rate generator reset bit.
You can use GRST to take the McBSP sample rate generator into and out of its reset state. This bit has a negative polarity
GRST = 0 indicates the reset state.

Reset type: SYSRSn


0h (R/W) = If you read a 0, the sample rate generator is in its reset state.
If you write a 0, you reset the sample rate generator.
If GRST = 0 due to a reset, CLKG is driven by the CPU clock divided by 2, and FSG is driven low (inactive). If GRST = 0 due to program code, CLKG and FSG are both driven low (inactive).
1h (R/W) = If you read a 1, the sample rate generator is enabled.
If you write a 1, you enable the sample rate generator by taking it out of its reset state.
When enabled, the sample rate generator generates the clock signal CLKG as programmed in the sample rate generator registers. If FRST = 1, the generator also generates the frame-synchronization signal FSG as programmed in the sample rate generator registers.
5-4XINTMR/W0hTransmit interrupt mode bits.
XINTM determines which event in the McBSP transmitter generates a transmit interrupt (XINT) request. If XINT is properly enabled, the CPU services the interrupt request
otherwise, the CPU ignores the request.

Reset type: SYSRSn


0h (R/W) = The McBSP sends a transmit interrupt (XINT) request to the CPU when the XRDY bit changes from 0 to 1, indicating that transmitter is ready to accept new data (the content of DXR[1,2] has been copied to XSR[1,2]).
Regardless of the value of XINTM, you can check XRDY to determine whether a word transfer is complete.
The McBSP sends an XINT request to the CPU when 16 enabled bits have been transmitted on the DX pin.
1h (R/W) = In the multichannel selection mode, the McBSP sends an XINT request to the CPU after every 16- channel block is transmitted in a frame.
Outside of the multichannel selection mode, no interrupt request is sent.
2h (R/W) = The McBSP sends an XINT request to the CPU when each transmit frame-synchronization pulse is detected. The interrupt request is sent even if the transmitter is in its reset state.
3h (R/W) = The McBSP sends an XINT request to the CPU when the XSYNCERR bit is set, indicating a transmit frame-synchronization error.
Regardless of the value of XINTM, you can check XSYNCERR to determine whether a transmit framesynchronization error occurred.
3XSYNCERRR/W0hTransmit frame-synchronization error bit.
XSYNCERR is set when a transmit frame-synchronization error is detected by the McBSP. If XINTM = 11b, the McBSP sends a transmit interrupt (XINT) request to the CPU when XSYNCERR is set. The flag remains set until you write a 0 to it or reset the transmitter.

Reset type: SYSRSn


0h (R/W) = No error
1h (R/W) = Transmit frame-synchronization error
2XEMPTYR0hTransmitter empty bit.
XEMPTY is cleared when the transmitter is ready to send new data but no new data is available (transmitter-empty condition). This bit has a negative polarity
a transmitter-empty condition is indicated by XEMPTY = 0.

Reset type: SYSRSn


0h (R/W) = Transmitter-empty condition
Typically this indicates that all the bits of the current word have been transmitted but there is no new
data in DXR1. XEMPTY is also cleared if the transmitter is reset and then restarted.
1h (R/W) = No transmitter-empty condition
1XRDYR0hTransmitter ready bit.
XRDY is set when the transmitter is ready to accept new data in DXR[1,2]. Specifically, XRDY is set in response to a copy from DXR1 to XSR1.
If the transmit interrupt mode is XINTM = 00b, the McBSP sends a transmit interrupt (XINT) request to the CPU when XRDY changes from 0 to 1.
Also, when XRDY changes from 0 to 1, the McBSP sends a transmit synchronization event (XEVT) signal to the DMA controller.

Reset type: SYSRSn


0h (R/W) = Transmitter not ready
When DXR1 is loaded, XRDY is automatically cleared.
1h (R/W) = Transmitter ready: DXR[1,2] is ready to accept new data.
If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both DXRs are copied to the transmit shift registers (XSRs), as described in the next step. If DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2
0XRSTR/W0hTransmitter reset bit. You can use XRST to take the McBSP transmitter into and out of its reset state. This bit has a negative polarity
XRST = 0 indicates the reset state.
To read about the effects of a transmitter reset, see Section 15.10.2, Resetting and Initializing a McBSP.

Reset type: SYSRSn


0h (R/W) = If you read a 0, the transmitter is in its reset state.
If you write a 0, you reset the transmitter.
1h (R/W) = If you read a 1, the transmitter is enabled.
If you write a 1, you enable the transmitter by taking it out of its reset state.

34.16.2.6 SPCR1 Register (Offset = 5h) [Reset = 0000h]

SPCR1 is shown in Figure 34-72 and described in Table 34-84.

Return to the Summary Table.

SPCR1 contains control and status bits for various McBSP functions such as digital loopback, receive data justification, clock stop mode, receive interrupt mode, DX pin delay enabler, receiver status bits, and receiver reset control.

Figure 34-72 SPCR1 Register
15141312111098
DLBRJUSTCLKSTPRESERVED
R/W-0hR/W-0hR/W-0hR-0h
76543210
DXENARESERVEDRINTMRSYNCERRRFULLRRDYRRST
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR/W-0h
Table 34-84 SPCR1 Register Field Descriptions
BitFieldTypeResetDescription
15DLBR/W0hDigital loopback mode bit.
DLB disables or enables the digital loopback mode of the McBSP:

Reset type: SYSRSn


0h (R/W) = Disabled
Internal DR is supplied by the MDRx pin. Internal FSR and internal MCLKR can be supplied by their respective pins or by the sample rate generator, depending on the mode bits FSRM and CLKRM.
Internal DX is supplied by the MDXx pin. Internal FSX and internal CLKX are supplied by their respective pins or are generated internally, depending on the mode bits FSXM and CLKXM.
1h (R/W) = Enabled
Internal receive signals are supplied by internal transmit signals:
MDRx connected to MDXx
MFSRx connected to MFSXx
MCLKR connected to MCLKXx
This mode allows you to test serial port code with a single DSP. The McBSP transmitter directly supplies data, frame synchronization, and clocking to the McBSP receiver.
14-13RJUSTR/W0hReceive sign-extension and justification mode bits.
During reception, RJUST determines how data is justified and bit filled before being passed to the data receive registers (DRR1, DRR2). RJUST is ignored if you enable a companding mode with the RCOMPAND bits. In a companding mode, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1.

Reset type: SYSRSn


0h (R/W) = Right justify the data and zero fill the MSBs
1h (R/W) = Right justify the data and sign-extend the data into the MSBs
2h (R/W) = Left justify the data and zero fill the LSBs
3h (R/W) = Reserved (do not use)
12-11CLKSTPR/W0hClock stop mode bits.
CLKSTP allows you to use the clock stop mode to support the SPI masterslave protocol. If you will not be using the SPI protocol, you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of eachdata transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b).

Reset type: SYSRSn


0h (R/W) = Clock stop mode is disabled.
1h (R/W) = Clock stop mode is disabled.
2h (R/W) = Clock stop mode, without clock delay
3h (R/W) = Clock stop mode, with half-cycle clock delay
10-8RESERVEDR0hReserved
7DXENAR/W0hDX delay enabler mode bit.
DXENA controls the delay enabler for the DX pin. The enabler creates an extra delay for turn-on time (for the length of the delay, see the device-specific data sheet).

Reset type: SYSRSn


0h (R/W) = DX delay enabler off
1h (R/W) = DX delay enabler on
6RESERVEDR/W0hReserved
5-4RINTMR/W0hReceive interrupt mode bits.
RINTM determines which event in the McBSP receiver generates areceive interrupt (RINT) request. If RINT is properly enabled inside the CPU, the CPU services the interrupt request
otherwise, the CPU ignores the request.

Reset type: SYSRSn


0h (R/W) = The McBSP sends a receive interrupt (RINT) request to the CPU when the RRDY bit changes from 0 to 1, indicating that receive data is ready to be read (the content of RBR[1,2] has been copied to DRR[1,2]):
Regardless of the value of RINTM, you can check RRDY to determine whether a word transfer is complete.
The McBSP sends a RINT request to the CPU when 16 enabled bits have been received on the DR pin.
1h (R/W) = In the multichannel selection mode, the McBSP sends a RINT request to the CPU after every 16- channel block is received in a frame.
Outside of the multichannel selection mode, no interrupt request is sent.
2h (R/W) = The McBSP sends a RINT request to the CPU when each receive frame-synchronization pulse is detected. The interrupt request is sent even if the receiver is in its reset state.
3h (R/W) = The McBSP sends a RINT request to the CPU when the RSYNCERR bit is set, indicating a receive frame-synchronization error.
Regardless of the value of RINTM, you can check RSYNCERR to determine whether a receive frame-synchronization error occurred.
3RSYNCERRR/W0hReceive frame-sync error bit.
RSYNCERR is set when a receive frame-sync error is detected by the McBSP. If RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU when RSYNCERR is set. The flag remains set until you write a 0 to it or reset the receiver.

Reset type: SYSRSn


0h (R/W) = No error
1h (R/W) = Receive frame-synchronization error.
2RFULLR0hReceiver full bit.
RFULL is set when the receiver is full with new data and the previously received data has not been read (receiver-full condition). For more details about this condition,

Reset type: SYSRSn


0h (R/W) = No receiver-full condition
1h (R/W) = Receiver-full condition: RSR[1,2] and RBR[1,2] are full with new data, but the previous data in DRR[1,2] has not been read
1RRDYR0hReceiver ready bit.
RRDY is set when data is ready to be read from DRR[1,2]. Specifically, RRDY is set in response to a copy from RBR1 to DRR1.
If the receive interrupt mode is RINTM = 00b, the McBSP sends a receive interrupt request to the CPU when RRDY changes from 0 to 1.
Also, when RRDY changes from 0 to 1, the McBSP sends a receive synchronization event (REVT) signal to the DMA controller.

Reset type: SYSRSn


0h (R/W) = Receiver not ready
When the content of DRR1 is read, RRDY is automatically cleared.
1h (R/W) = Receiver ready: New data can be read from DRR[1,2].
Important: If both DRRs are required (word length larger than 16 bits), the CPU or the DMA controller must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.
0RRSTR/W0hReceiver reset bit.
You can use RRST to take the McBSP receiver into and out of its reset state. This bit has a negative polarity
RRST = 0 indicates the reset state.

Reset type: SYSRSn


0h (R/W) = If you read a 0, the receiver is in its reset state.
If you write a 0, you reset the receiver.
1h (R/W) = If you read a 1, the receiver is enabled.
If you write a 1, you enable the receiver by taking it out of its reset state.

34.16.2.7 RCR2 Register (Offset = 6h) [Reset = 0000h]

RCR2 is shown in Figure 34-73 and described in Table 34-85.

Return to the Summary Table.

RCR2 contains control bits for the receiver such as number of phases in each frame, the serial word length and number of words for phase 2 of dual phase frames, receive companding mode, receive frame synchronization ignore function, and the receive data delay.

Figure 34-73 RCR2 Register
15141312111098
RPHASERFRLEN2
R/W-0hR/W-0h
76543210
RWDLEN2RCOMPANDRFIGRDATDLY
R/W-0hR/W-0hR/W-0hR/W-0h
Table 34-85 RCR2 Register Field Descriptions
BitFieldTypeResetDescription
15RPHASER/W0hReceive phase number bit.
RPHASE determines whether the receive frame has one phase or two phases. For each phase you can define the serial word length and the number of serial words in the phase. To set up phase 1, program RWDLEN1 (word length) and RFRLEN1 (number of words). To set up phase 2 (if there are two phases), program RWDLEN2 and RFRLEN2.

Reset type: SYSRSn


0h (R/W) = Single-phase frame
The receive frame has only one phase, phase 1.
1h (R/W) = Dual-phase frame
The receive frame has two phases, phase 1 and phase 2.
14-8RFRLEN2R/W0hReceive frame length 2 (1 to 128 words). Each frame of receive data can have one or two phases,
depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1 in RCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dual-phase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the frame, and RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit RFRLEN fields allow up to 128 words per phase. See Table 15-77 for a summary of how to determine the frame length. This length corresponds to the number of words or logical time slots or channels per frame-synchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For example, if you want a phase length of 128 words in phase 2, load 127 into RFRLEN2.

Reset type: SYSRSn

7-5RWDLEN2R/W0hReceive word length 2. Each frame of receive data can have one or two phases, depending on the
value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1
selects the length for every serial word received in the frame. If a dual-phase frame is selected,
RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 in RCR2
determines the word length in phase 2 of the frame.

Reset type: SYSRSn


0h (R/W) = 8 bits
1h (R/W) = 12 bits
2h (R/W) = 16 bits
3h (R/W) = 20 bits
4h (R/W) = 24 bits
5h (R/W) = 32 bits
6h (R/W) = Reserved (do not use)
7h (R/W) = Reserved (do not use)
4-3RCOMPANDR/W0hReceive companding mode bits.
Companding (COMpress and exPAND) hardware allows compression and expansion of data in either u-law or A-law format.
RCOMPAND allows you to choose one of the following companding modes for the McBSP receiver:
For more details about these companding modes, see Section 15.1.5, Companding (Compressing and Expanding) Data.

Reset type: SYSRSn


0h (R/W) = No companding, any size data, MSB received first
1h (R/W) = No companding, 8-bit data, LSB received first
2h (R/W) = u-law companding, 8-bit data, MSB received first
3h (R/W) = A-law companding, 8-bit data, MSB received first
2RFIGR/W0hReceive frame-synchronization ignore bit. If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully received, this pulse is treated as an unexpected framesynchronization pulse. Unexpected Receive Frame-Synchronization Pulse.
Setting RFIG causes the serial port to ignore unexpected frame-synchronization signals during reception.

Reset type: SYSRSn


0h (R/W) = Frame-synchronization detect. An unexpected FSR pulse causes the receiver to discard the contents of RSR[1,2] in favor of the new incoming data. The receiver:
1. Aborts the current data transfer
2. Sets RSYNCERR in SPCR1
3. Begins the transfer of a new data word
1h (R/W) = Frame-synchronization ignore. An unexpected FSR pulse is ignored. Reception continues uninterrupted.
1-0RDATDLYR/W0hReceive data delay bits.
RDATDLY specifies a data delay of 0, 1, or 2 receive clock cycles after framesynchronization and before the reception of the first bit of the frame.

Reset type: SYSRSn


0h (R/W) = 0-bit data delay
1h (R/W) = 1-bit data delay
2h (R/W) = 2-bit data delay
3h (R/W) = Reserved (do not use)

34.16.2.8 RCR1 Register (Offset = 7h) [Reset = 0000h]

RCR1 is shown in Figure 34-74 and described in Table 34-86.

Return to the Summary Table.

RCR1 contains control bits for the receiver such as the serial word length and number of words for single phase transmissions, or phase 1 if dual phase frames are used.

Figure 34-74 RCR1 Register
15141312111098
RESERVEDRFRLEN1
R-0hR/W-0h
76543210
RWDLEN1RESERVED
R/W-0hR-0h
Table 34-86 RCR1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14-8RFRLEN1R/W0hReceive frame length 1 (1 to 128 words).
Each frame of receive data can have one or two phases,depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1 inRCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dualphase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the frame, and RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit RFRLEN fields allow up to 128 words per phase. See Table 15-75 for a summary of how you determine the frame length. This length corresponds to the number of words or logical time slots or channels per framesynchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.

Note: When operating in SPI mode, the frame length can only be 1 word.

Reset type: SYSRSn

7-5RWDLEN1R/W0hReceive word length 1.
Each frame of receive data can have one or two phases, depending on the value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1 selects the length for every serial word received in the frame. If a dual-phase frame is selected, RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 in RCR2 determines the word length in phase 2 of the frame.

Reset type: SYSRSn


0h (R/W) = 8 bits
1h (R/W) = 12 bits
2h (R/W) = 16 bits
3h (R/W) = 20 bits
4h (R/W) = 24 bits
5h (R/W) = 32 bits
6h (R/W) = Reserved (do not use)
7h (R/W) = Reserved (do not use)
4-0RESERVEDR0hReserved

34.16.2.9 XCR2 Register (Offset = 8h) [Reset = 0000h]

XCR2 is shown in Figure 34-75 and described in Table 34-87.

Return to the Summary Table.

XCR2 contains control bits for the transmitter such as number of phases in each frame, the serial word length and number of words for phase 2 of dual phase frames, transmit companding mode, transmit frame synchronization ignore function, and the transmit data delay control.

Figure 34-75 XCR2 Register
15141312111098
XPHASEXFRLEN2
R/W-0hR/W-0h
76543210
XWDLEN2XCOMPANDXFIGXDATDLY
R/W-0hR/W-0hR/W-0hR/W-0h
Table 34-87 XCR2 Register Field Descriptions
BitFieldTypeResetDescription
15XPHASER/W0hTransmit phase number bit.
XPHASE determines whether the transmit frame has one phase or two phases. For each phase you can define the serial word length and the number of serial words in the phase. To set up phase 1, program XWDLEN1 (word length) and XFRLEN1 (number of words). To set up phase 2 (if there are two phases), program XWDLEN2 and XFRLEN2.

Reset type: SYSRSn

14-8XFRLEN2R/W0hTransmit frame length 2 (1 to 128 words).
Each frame of transmit data can have one or two phases, depending on value that you load into the XPHASE bit. If a single-phase frame is selected, XFRLEN1 in XCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dualphase frame is selected, XFRLEN1 determines the number of serial words in phase 1 of the frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame. The 7-bit XFRLEN fields
allow up to 128 words per phase. See Table 15-81 for a summary of how to determine the frame length. This length corresponds to the number of words or logical time slots or channels per framesynchronization period.
Program the XFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into XFRLEN1.

Reset type: SYSRSn

7-5XWDLEN2R/W0hTransmit word length 2.
Each frame of transmit data can have one or two phases, depending on the value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1 selects the length for every serial word transmitted in the frame. If a dual-phase frame is selected, XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 in XCR2 determines the word length in phase 2 of the frame.

Reset type: SYSRSn


0h (R/W) = 8 bits
1h (R/W) = 12 bits
2h (R/W) = 16 bits
3h (R/W) = 20 bits
4h (R/W) = 24 bits
5h (R/W) = 32 bits
6h (R/W) = Reserved (do not use)
7h (R/W) = Reserved (do not use)
4-3XCOMPANDR/W0hTransmit companding mode bits.
Companding (COMpress and exPAND) hardware allows compression and expansion of data in either u-law or A-law format.

Reset type: SYSRSn


0h (R/W) = No companding, any size data, MSB received first
1h (R/W) = No companding, 8-bit data, LSB received first
2h (R/W) = u-law companding, 8-bit data, MSB received first
3h (R/W) = A-law companding, 8-bit data, MSB received first
2XFIGR/W0hTransmit frame-synchronization ignore bit.
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully transmitted, this pulse is treated as an unexpected framesynchronization pulse.
Setting XFIG causes the serial port to ignore unexpected frame-synchronization pulses during transmission.

Reset type: SYSRSn


0h (R/W) = Frame-synchronization detect. An unexpected FSX pulse causes the transmitter to discard the content of XSR[1,2]. The transmitter:
1. Aborts the present transmission
2. Sets XSYNCERR in SPCR2
3. Begins a new transmission from DXR[1,2]. If new data was written to DXR[1,2] since the last DXR[1,2]-to-XSR[1,2] copy, the current value in XSR[1,2] is lost. Otherwise, the same data is transmitted.
1h (R/W) = Frame-synchronization ignore. An unexpected FSX pulse is ignored. Transmission continues uninterrupted.
1-0XDATDLYR/W0hTransmit data delay bits. XDATDLY specifies a data delay of 0, 1, or 2 transmit clock cycles after frame synchronization and before the transmission of the first bit of the frame.

Reset type: SYSRSn


0h (R/W) = 0-bit data delay
1h (R/W) = 1-bit data delay
2h (R/W) = 2-bit data delay
3h (R/W) = Reserved (do not use)

34.16.2.10 XCR1 Register (Offset = 9h) [Reset = 0000h]

XCR1 is shown in Figure 34-76 and described in Table 34-88.

Return to the Summary Table.

XCR1 contains control bits for the transmitter such as the serial word length and number of words for single phase transmissions, or phase 1 if dual phase frames are used.

Figure 34-76 XCR1 Register
15141312111098
RESERVEDXFRLEN1
R-0hR/W-0h
76543210
XWDLEN1RESERVED
R/W-0hR-0h
Table 34-88 XCR1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14-8XFRLEN1R/W0hTransmit frame length 1 (1 to 128 words). Each frame of transmit data can have one or two phases, depending on value that you load into the XPHASE bit. If a single-phase frame is selected, XFRLEN1 in XCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dual-phase frame is selected, XFRLEN1 determines the number of serial words in phase 1 of the
frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame. The 7-bit XFRLEN fields allow up to 128 words per phase. See Table 15-79 for a summary of how you determine the frame length. This length corresponds to the number of words or logical time slots or channels per frame-synchronization period. Program the XFRLEN fields with [w minus 1], where w represents the number of words per phase. For example, if you want a phase length of 128 words in phase 1, load 127 into XFRLEN1.

Note: When operating in SPI mode, the frame length can only be 1 word.

Reset type: SYSRSn

7-5XWDLEN1R/W0hTransmit word length 1.
Each frame of transmit data can have one or two phases, depending on the value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1 selects the length for every serial word transmitted in the frame. If a dual-phase frame is selected, XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 in XCR2 determines the word length in phase 2 of the frame.

Reset type: SYSRSn


0h (R/W) = 8 bits
1h (R/W) = 12 bits
2h (R/W) = 16 bits
3h (R/W) = 20 bits
4h (R/W) = 24 bits
5h (R/W) = 32 bits
6h (R/W) = Reserved (do not use)
7h (R/W) = Reserved (do not use)
4-0RESERVEDR0hReserved

34.16.2.11 SRGR2 Register (Offset = Ah) [Reset = 0000h]

SRGR2 is shown in Figure 34-77 and described in Table 34-89.

Return to the Summary Table.

SRGR2 contains control bits for the sample rate generator such as input clock selection, internal tranmist frame-synchronization source selection, and the period between frame-synchronization pulses.
If an external source provides the input clock source for the sample rate generator, a control bit is provided to make the CLKG synchronized to an external frame synchronization pulse on the FSR pin so that CLKG is kept in phase with the input clock.

Figure 34-77 SRGR2 Register
15141312111098
GSYNCRESERVEDCLKSMFSGMFPER
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
FPER
R/W-0h
Table 34-89 SRGR2 Register Field Descriptions
BitFieldTypeResetDescription
15GSYNCR/W0hClock synchronization mode bit for CLKG.
GSYNC is used only when the input clock source for the sample rate generator is external?on the MCLKR pin.
When GSYNC = 1, the clock signal (CLKG) and the frame-synchronization signal (FSG) generated by the sample rate generator are made dependent on pulses on the FSR pin.

Reset type: SYSRSn


0h (R/W) = No clock synchronization
CLKG oscillates without adjustment, and FSG pulses every (FPER + 1) CLKG cycles.
1h (R/W) = Clock synchronization
- CLKG is adjusted as necessary so that it is synchronized with the input clock on the
MCLKR pin.
- FSG pulses. FSG only pulses in response to a pulse on the FSR pin.
The frame-synchronization period defined in FPER is ignored.
14RESERVEDR/W0hReserved
13CLKSMR/W0hSample rate generator mode

Reset type: SYSRSn


0h (R/W) = Sample rate generator input clock mode bit. The sample rate generator can accept an input clock signal and divide it down according to CLKGDV to produce an output clock signal, CLKG. The frequency of CLKG is:)
CLKG frequency = (input clock frequency)/ (CLKGDV + 1
CLKSM is used in conjunction with the SCLKME bit to determine the source for the input clock.

A reset selects the CPU clock as the input clock and forces the CLKG frequency to half the LSPCLK frequency.
The input clock for the sample rate generator is taken from the MCLKR pin, depending on the value of the SCLKME bit of PCR:
SCLKME CLKSM Input Clock For
Sample Rate Generator
0 0 Reserved
1 0 Signal on MCLKR pin
1h (R/W) = The input clock for the sample rate generator is taken from the LSPCLK or from the MCLKX pin, depending on the value of the SCLKME bit of PCR:
SCLKME CLKSM Input Clock For
Sample Rate Generator
0 1 LSPCLK
1 1 Signal on MCLKX pin
12FSGMR/W0hSample rate generator transmit frame-synchronization mode bit.
The transmitter can get frame synchronization from the FSX pin (FSXM = 0) or from inside the McBSP (FSXM = 1). When FSXM = 1, the FSGM bit determines how the McBSP supplies frame-synchronization pulses.

Reset type: SYSRSn


0h (R/W) = If FSXM = 1, the McBSP generates a transmit frame-synchronization pulse when the content of DXR[1,2] is copied to XSR[1,2].
1h (R/W) = If FSXM = 1, the transmitter uses frame-synchronization pulses generated by the sample rate generator. Program the FWID bits to set the width of each pulse. Program the FPER bits to set the period between pulses.
11-0FPERR/W0hFrame-synchronization period bits for FSG.
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. The period between framesynchronization pulses on FSG is (FPER + 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles:

Reset type: SYSRSn

34.16.2.12 SRGR1 Register (Offset = Bh) [Reset = 0001h]

SRGR1 is shown in Figure 34-78 and described in Table 34-90.

Return to the Summary Table.

SRGR1 contains control bits for the sample rate generator functions such as the divide down frequency, and the width fo the frame-synchronization pulses on FSG.

Figure 34-78 SRGR1 Register
15141312111098
FWID
R/W-0h
76543210
CLKGDV
R/W-1h
Table 34-90 SRGR1 Register Field Descriptions
BitFieldTypeResetDescription
15-8FWIDR/W0hDivide-down value for CLKG.
The sample rate generator can accept an input clock signal and divide it down according to CLKGDV to produce an output clock signal, CLKG. The frequency of CLKG is:
CLKG frequency = (Input clock frequency)/ (CLKGDV + 1)
The input clock is selected by the SCLKME and CLKSM bits:
SCLKME CLKSM Input Clock For
Sample Rate Generator
0 0 Reserved
0 1 LSPCLK
1 0 Signal on MCLKR pin
1 1 Signal on MCLKX pin

Reset type: SYSRSn

7-0CLKGDVR/W1hFrame-synchronization pulse width bits for FSG
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. For frame-synchronization pulses on FSG, (FWID + 1) is the pulse width in CLKG cycles. The eight bits of FWID allow a pulse width of 1 to 256 CLKG cycles:
0 <= FWID <= 255
1 <= (FWID + 1) <= 256 CLKG cycles
The period between the frame-synchronization pulses on FSG is defined by the FPER bits.

Reset type: SYSRSn

34.16.2.13 MCR2 Register (Offset = Ch) [Reset = 0000h]

MCR2 is shown in Figure 34-79 and described in Table 34-91.

Return to the Summary Table.

MCR2 contains control bits for the transmitter multi-channel functions such as channel enable mode selection, channel partition modes, channel block assignments, and active channel status bits.

Figure 34-79 MCR2 Register
15141312111098
RESERVEDXMCMEXPBBLK
R-0hR/W-0hR/W-0h
76543210
XPBBLKXPABLKXCBLKXMCM
R/W-0hR/W-0hR-0hR/W-0h
Table 34-91 MCR2 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9XMCMER/W0hTransmit multichannel partition mode bit.
XMCME determines whether only 32 channels or all 128
channels are to be individually selectable. XMCME is only applicable if channels can be individually disabled/enabled or masked/unmasked for transmission (XMCM is nonzero).

Reset type: SYSRSn

8-7XPBBLKR/W0hTransmit partition B block bits

XPBBLK is only applicable if channels can be individually disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0). Under these conditions, the McBSP transmitter can transmit or withhold data in any of the 32 channels that are assigned to
partitions A and B of the transmitter.
The 128 transmit channels of the McBSP are divided equally among 8 blocks (0 through 7). When XPBBLK is applicable, use XPBBLK to assign one of the odd-numbered blocks (1, 3, 5, or 7) to partition B, as shown in the following table. Use the PABLK bit to assign one of the evennumbered blocks (0, 2, 4, or 6) to partition A.
If you want to use more than 32 channels, you can change block assignments dynamically. You can assign a new block to one partition while the transmitter is handling activity in the other partition. For example, while the block in partition A is active, you can change which block is assigned to partition B. The XCBLK bits are regularly pdated to indicate which block is active.
When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the receive block bits (RPABLK and RPBBLK) rather than the transmit block bits (XPABLK and XPBBLK).

Reset type: SYSRSn


0h (R/W) = Block 1: channels 16 through 31
1h (R/W) = Block 3: channels 48 through 63
2h (R/W) = Block 5: channels 80 through 95
3h (R/W) = Block 7: channels 112 through 127
6-5XPABLKR/W0hTransmit partition A block bits.
XPABLK is only applicable if channels can be individually disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0). Under these conditions, the McBSP transmitter can transmit or withhold data in any of the 32 channels that are assigned to artitions A and B of the transmitter. See the Descriptionfor XPBBLK (bits 8-7) for more information about assigning blocks to partitions A and B.

Reset type: SYSRSn


0h (R/W) = Block 0: channels 0 through 15
1h (R/W) = Block 2: channels 32 through 47
2h (R/W) = Block 4: channels 64 through 79
3h (R/W) = Block 6: channels 96 through 111
4-2XCBLKR0hTransmit current block indicator.
XCBLK indicates which block of 16 channels is involved in the current McBSP transmission:

Reset type: SYSRSn


0h (R/W) = Block 0: channels 0 through 15
1h (R/W) = Block 1: channels 16 through 31
2h (R/W) = Block 2: channels 32 through 47
3h (R/W) = Block 3: channels 48 through 63
4h (R/W) = Block 4: channels 64 through 79
5h (R/W) = Block 5: channels 80 through 95
6h (R/W) = Block 6: channels 96 through 111
7h (R/W) = Block 7: channels 112 through 127
1-0XMCMR/W0hTransmit multichannel selection mode bits.
XMCM determines whether all channels or only selected channels are enabled and unmasked for transmission.

Reset type: SYSRSn


0h (R/W) = No transmit multichannel selection mode is on. All channels are enabled and unmasked. No channels can be disabled or masked
1h (R/W) = All channels are disabled unless they are selected in the appropriate transmit channel enable registers (XCERs). If enabled, a channel in this mode is also unmasked.
The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs.
2h (R/W) = All channels are enabled, but they are masked unless they are selected in the appropriate transmit channel enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs.
3h (R/W) = This mode is used for symmetric transmission and reception.
All channels are disabled for transmission unless they are enabled for reception in the appropriate receive channel enable registers (RCERs). Once enabled, they are masked unless they are also selected in the appropriate transmit channel enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128 channels are selectable in RCERs and XCERs.

34.16.2.14 MCR1 Register (Offset = Dh) [Reset = 0000h]

MCR1 is shown in Figure 34-80 and described in Table 34-92.

Return to the Summary Table.

MCR1 contains control bits for the receiver multi-channel functions such as channel enable mode selection, channel partition modes, channel block assignments, and active channel status bits.

Figure 34-80 MCR1 Register
15141312111098
RESERVEDRMCMERPBBLK
R-0hR/W-0hR/W-0h
76543210
RPBBLKRPABLKRCBLKRESERVEDRMCM
R/W-0hR/W-0hR-0hR/W-0hR/W-0h
Table 34-92 MCR1 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9RMCMER/W0hReceive multichannel partition mode bit.
RMCME is only applicable if channels can be individually enabled or disabled for reception (RMCM = 1).
RMCME determines whether only 32 channels or all 128 channels are to be individually selectable.

Reset type: SYSRSn


0h (R/W) = 2-partition mode
Only partitions A and B are used. You can control up to 32 channels in the receive multichannel selection mode (RMCM = 1).
Assign 16 channels to partition A with the RPABLK bits.
Assign 16 channels to partition B with the RPBBLK bits.
You control the channels with the appropriate receive channel enable registers:
RCERA: Channels in partition A
RCERB: Channels in partition B
1h (R/W) = 8-partition mode
All partitions (A through H) are used. You can control up to 128 channels in the receive multichannel selection mode. You control the channels with the appropriate receive channel enable registers:
RCERA: Channels 0 through 15
RCERB: Channels 16 through 31
RCERC: Channels 32 through 47
RCERD: Channels 48 through 63
RCERE: Channels 64 through 79
RCERF: Channels 80 through 95
RCERG: Channels 96 through 111
RCERH: Channels 112 through 127
8-7RPBBLKR/W0hReceive partition B block bits
RPBBLK is only applicable if channels can be individually enabled or disabled (RMCM = 1) and the 2-partition mode is selected (RMCME = 0). Under these conditions, the McBSP receiver can accept or ignore data in any of the 32 channels that are assigned to partitions A and B of the receiver.
The 128 receive channels of the McBSP are divided equally among 8 blocks (0 through 7). When RPBBLK is applicable, use RPBBLK to assign one of the odd-numbered blocks (1, 3, 5, or 7) to partition B. Use the RPABLK bits to assign one of the even-numbered blocks (0, 2, 4, or 6) to partition A.
If you want to use more than 32 channels, you can change block assignments dynamically. You can assign a new block to one partition while the receiver is handling activity in the other partition. For example, while the block in partition A is active, you can change which block is assigned to partition B. The RCBLK bits are regularly updated to indicate which block is active.
When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the receive block bits (RPABLK and RPBBLK) rather than the transmit block bits (XPABLK and XPBBLK).

Reset type: SYSRSn


0h (R/W) = Block 1: channels 16 through 31
1h (R/W) = Block 3: channels 48 through 63
2h (R/W) = Block 5: channels 80 through 95
3h (R/W) = Block 7: channels 112 through 127
6-5RPABLKR/W0hReceive partition A block bits
RPABLK is only applicable if channels can be individually enabled or disabled (RMCM = 1) and the 2-partition mode is selected (RMCME = 0). Under these conditions, the McBSP receiver can accept or ignore data in any of the 32 channels that are assigned to partitions A and B of the receiver. See the Descriptionfor RPBBLK (bits 8-7) for more information about assigning blocks to partitions A and B.

Reset type: SYSRSn


0h (R/W) = Block 0: channels 0 through 15
1h (R/W) = Block 2: channels 32 through 47
2h (R/W) = Block 4: channels 64 through 79
3h (R/W) = Block 6: channels 96 through 111
4-2RCBLKR0hReceive current block indicator.
RCBLK indicates which block fo 16 channels is involved in the current McBSP reception

Reset type: SYSRSn


0h (R/W) = Block 0: channels 0 through 15
1h (R/W) = Block 1: channels 16 through 31
2h (R/W) = Block 2: channels 32 through 47
3h (R/W) = Block 3: channels 48 through 63
4h (R/W) = Block 4: channels 64 through 79
5h (R/W) = Block 5: channels 80 through 95
6h (R/W) = Block 6: channels 96 through 111
7h (R/W) = Block 7: channels 112 through 127
1RESERVEDR/W0hReserved
0RMCMR/W0hReceive multichannel selection mode bit. RMCM determines whether all channels or only selected channels are enabled for reception:

Reset type: SYSRSn


0h (R/W) = All 128 channels are enabled.
1h (R/W) = Multichanneled selection mode. Channels can be individually enabled or disabled.
The only channels enabled are those selected in the appropriate receive channel enable registers (RCERs). The way channels are assigned to the RCERs depends on the number of receive
channel partitions (2 or 8), as defined by the RMCME bit.

34.16.2.15 RCERA Register (Offset = Eh) [Reset = 0000h]

RCERA is shown in Figure 34-81 and described in Table 34-93.

Return to the Summary Table.

RCERA contains the receive channel enable registers for the A partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-81 RCERA Register
15141312111098
RCEA
R/W-0h
76543210
RCEA
R/W-0h
Table 34-93 RCERA Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEAR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.16 RCERB Register (Offset = Fh) [Reset = 0000h]

RCERB is shown in Figure 34-82 and described in Table 34-94.

Return to the Summary Table.

RCERB contains the receive channel enable registers for the B partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-82 RCERB Register
15141312111098
RCEB
R/W-0h
76543210
RCEB
R/W-0h
Table 34-94 RCERB Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEBR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.17 XCERA Register (Offset = 10h) [Reset = 0000h]

XCERA is shown in Figure 34-83 and described in Table 34-95.

Return to the Summary Table.

XCERA contains the transmit channel enable registers for the A partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-83 XCERA Register
15141312111098
XCERA
R/W-0h
76543210
XCERA
R/W-0h
Table 34-95 XCERA Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERAR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.18 XCERB Register (Offset = 11h) [Reset = 0000h]

XCERB is shown in Figure 34-84 and described in Table 34-96.

Return to the Summary Table.

XCERB contains the transmit channel enable registers for the B partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-84 XCERB Register
15141312111098
XCERB
R/W-0h
76543210
XCERB
R/W-0h
Table 34-96 XCERB Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERBR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.19 PCR Register (Offset = 12h) [Reset = 0000h]

PCR is shown in Figure 34-85 and described in Table 34-97.

Return to the Summary Table.

PCR contains control bits for the McBSP pins such as frame synchronization modes, clock modes, input clock source selection for the sample rate generator, frame synchronization pulse active polarity, and transmit/receive active edge selection.

Figure 34-85 PCR Register
15141312111098
RESERVEDFSXMFSRMCLKXMCLKRM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
SCLKMERESERVEDRESERVEDRESERVEDFSXPFSRPCLKXPCLKRP
R/W-0hR-0hR-0hR-0hR/W-0hR-0hR-0hR/W-0h
Table 34-97 PCR Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11FSXMR/W0hTransmit frame-synchronization mode bit.
FSXM determines whether transmit framesynchronization pulses are supplied externally or internally. The polarity of the signal on the FSX pin is determined by the FSXP bit.

Reset type: SYSRSn


0h (R/W) = Transmit frame synchronization is supplied by an external source via the FSX pin.
1h (R/W) = Transmit frame synchronization is generated internally by the Sample Rate generator, as determined by the FSGM bit of SRGR2
10FSRMR/W0hReceive frame-synchronization mode bit.
FSRM determines whether receive framesynchronization pulses are supplied externally or internally. The polarity of the signal on the FSR pin is determined by the FSRP bit.

Reset type: SYSRSn


0h (R/W) = Receive frame synchronization is supplied by an external source via the FSR pin.
1h (R/W) = Receive frame synchronization is supplied by the sample rate generator. FSR is an output pin reflecting internal FSR, except when GSYNC = 1 in SRGR2
9CLKXMR/W0hTransmit clock mode bit.
CLKXM determines whether the source for the transmit clock is external or internal, and whether the MCLKX pin is an input or an output. The polarity of the signal on the MCLKX pin is determined by the CLKXP bit.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI protocol. If the McBSP is a master, make sure that CLKX is an output. If the McBSP is a slave, make sure that CLKX is an input.

Reset type: SYSRSn


0h (R/W) = Not in clock stop mode (CLKSTP = 00b or 01b):
The transmitter gets its clock signal from an external source via the MCLKX pin.

In clock stop mode (CLKSTP = 10b or 11b):
The McBSP is a slave in the SPI protocol. The internal transmit clock (CLKX) is driven by the SPI master via the MCLKX pin. The internal receive clock (MCLKR) is driven internally by CLKX, so that both the transmitter and the receiver are controlled by the external master clock.
1h (R/W) = Not in clock stop mode (CLKSTP = 00b or 01b):
Internal CLKX is driven by the sample rate generator of the McBSP. The MCLKX pin is an output pin that reflects internal CLKX.

In clock stop mode (CLKSTP = 10b or 11b):
The McBSP is a master in the SPI protocol. The sample rate generator drives the internal transmit clock (CLKX). Internal CLKX is reflected on the MCLKX pin to drive the shift clock of the SPI-compliant slaves in the system. Internal CLKX also drives the internal receive clock (MCLKR), so that both the transmitter and the receiver are controlled by the internal master clock
8CLKRMR/W0hReceive clock mode bit.
The role of CLKRM and the resulting effect on the MCLKR pin depend on whether the McBSP is in the digital loopback mode (DLB = 1).
The polarity of the signal on the MCLKR pin is determined by the CLKRP bit.

Reset type: SYSRSn


0h (R/W) = Not in digital loopback mode (DLB = 0):
The MCLKR pin is an input pin that supplies the internal receive clock (MCLKR).

In digital loopback mode (DLB = 1):
The MCLKR pin is in the high impedance state. The internal receive clock (MCLKR) is driven by the internal transmit clock (CLKX). CLKX is derived according to the CLKXM bit.
1h (R/W) = Not in digital loopback mode (DLB = 0):
Internal MCLKR is driven by the sample rate generator of the McBSP. The MCLKR pin is an output pin that reflects internal MCLKR.

In digital loopback mode (DLB = 1):
Internal MCLKR is driven by internal CLKX. The MCLKR pin is an output pin that reflects internal MCLKR. CLKX is derived according to the CLKXM bit.
7SCLKMER/W0hSample rate generator input clock mode bit. The sample rate generator can produce a clock signal, CLKG. The frequency of CLKG is:
CLKG freq. = (Input clock frequency) / (CLKGDV + 1)
SCLKME is used in conjunction with the CLKSM bit to select the input clock.
SCLKME CLKSM Input Clock For
Sample Rate Generator
0 0 Reserved
0 1 LSPCLK
The input clock for the sample rate generator is taken from the MCLKR pin or from the MCLKX pin, depending on the value of the CLKSM bit of SRGR2:

SCLKME CLKSM Input Clock For
Sample Rate Generator
1 0 Signal on MCLKR pin
1 1 Signal on MCLKX pin

Reset type: SYSRSn

6RESERVEDR0hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3FSXPR/W0hTransmit frame-synchronization polarity bit. FSXP determines the polarity of FSX as seen on the FSX pin.

Reset type: SYSRSn


0h (R/W) = Transmit frame-synchronization pulses are active high.
1h (R/W) = Transmit frame-synchronization pulses are active low.
2FSRPR0hReceive frame-synchronization polarity bit. FSRP determines the polarity of FSR as seen on the FSR pin.

Reset type: SYSRSn


0h (R/W) = Receive frame-synchronization pulses are active high.
1h (R/W) = Receive frame-synchronization pulses are active low.
1CLKXPR0hTransmit clock polarity bit. CLKXP determines the polarity of CLKX as seen on the MCLKX pin.

Reset type: SYSRSn


0h (R/W) = Transmit data is sampled on the rising edge of CLKX.
1h (R/W) = Transmit data is sampled on the falling edge of CLKX.
0CLKRPR/W0hReceive clock polarity bit. CLKRP determines the polarity of CLKR as seen on the MCLKR pin.

Reset type: SYSRSn


0h (R/W) = Receive data is sampled on the falling edge of MCLKR.
1h (R/W) = Receive data is sampled on the rising edge of MCLKR.

34.16.2.20 RCERC Register (Offset = 13h) [Reset = 0000h]

RCERC is shown in Figure 34-86 and described in Table 34-98.

Return to the Summary Table.

RCERC contains the receive channel enable registers for the C partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-86 RCERC Register
15141312111098
RCEC
R/W-0h
76543210
RCEC
R/W-0h
Table 34-98 RCERC Register Field Descriptions
BitFieldTypeResetDescription
15-0RCECR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.21 RCERD Register (Offset = 14h) [Reset = 0000h]

RCERD is shown in Figure 34-87 and described in Table 34-99.

Return to the Summary Table.

RCERD contains the receive channel enable registers for the D partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-87 RCERD Register
15141312111098
RCED
R/W-0h
76543210
RCED
R/W-0h
Table 34-99 RCERD Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEDR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.22 XCERC Register (Offset = 15h) [Reset = 0000h]

XCERC is shown in Figure 34-88 and described in Table 34-100.

Return to the Summary Table.

XCERC contains the transmit channel enable registers for the C partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-88 XCERC Register
15141312111098
XCERC
R/W-0h
76543210
XCERC
R/W-0h
Table 34-100 XCERC Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERCR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.23 XCERD Register (Offset = 16h) [Reset = 0000h]

XCERD is shown in Figure 34-89 and described in Table 34-101.

Return to the Summary Table.

XCERD contains the transmit channel enable registers for the D partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-89 XCERD Register
15141312111098
XCERD
R/W-0h
76543210
XCERD
R/W-0h
Table 34-101 XCERD Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERDR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.24 RCERE Register (Offset = 17h) [Reset = 0000h]

RCERE is shown in Figure 34-90 and described in Table 34-102.

Return to the Summary Table.

RCERE contains the receive channel enable registers for the E partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-90 RCERE Register
15141312111098
RCEE
R/W-0h
76543210
RCEE
R/W-0h
Table 34-102 RCERE Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEER/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.25 RCERF Register (Offset = 18h) [Reset = 0000h]

RCERF is shown in Figure 34-91 and described in Table 34-103.

Return to the Summary Table.

RCERF contains the receive channel enable registers for the F partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-91 RCERF Register
15141312111098
RCEF
R/W-0h
76543210
RCEF
R/W-0h
Table 34-103 RCERF Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEFR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.26 XCERE Register (Offset = 19h) [Reset = 0000h]

XCERE is shown in Figure 34-92 and described in Table 34-104.

Return to the Summary Table.

XCERE contains the transmit channel enable registers for the E partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-92 XCERE Register
15141312111098
XCERE
R/W-0h
76543210
XCERE
R/W-0h
Table 34-104 XCERE Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERER/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.27 XCERF Register (Offset = 1Ah) [Reset = 0000h]

XCERF is shown in Figure 34-93 and described in Table 34-105.

Return to the Summary Table.

XCERF contains the transmit channel enable registers for the F partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-93 XCERF Register
15141312111098
XCERF
R/W-0h
76543210
XCERF
R/W-0h
Table 34-105 XCERF Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERFR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.28 RCERG Register (Offset = 1Bh) [Reset = 0000h]

RCERG is shown in Figure 34-94 and described in Table 34-106.

Return to the Summary Table.

RCERG contains the receive channel enable registers for the G partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-94 RCERG Register
15141312111098
RCEG
R/W-0h
76543210
RCEG
R/W-0h
Table 34-106 RCERG Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEGR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.29 RCERH Register (Offset = 1Ch) [Reset = 0000h]

RCERH is shown in Figure 34-95 and described in Table 34-107.

Return to the Summary Table.

RCERH contains the receive channel enable registers for the H partition. This register is only used when the receiver is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. RMCM is nonzero).

Figure 34-95 RCERH Register
15141312111098
RCEH
R/W-0h
76543210
RCEH
R/W-0h
Table 34-107 RCERH Register Field Descriptions
BitFieldTypeResetDescription
15-0RCEHR/W0hReceive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

Reset type: SYSRSn


0h (R/W) = Disable the channel that is mapped to RCEx.
1h (R/W) = Enable the channel that is mapped to RCEx.

34.16.2.30 XCERG Register (Offset = 1Dh) [Reset = 0000h]

XCERG is shown in Figure 34-96 and described in Table 34-108.

Return to the Summary Table.

XCERG contains the transmit channel enable registers for the G partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-96 XCERG Register
15141312111098
XCERG
R/W-0h
76543210
XCERG
R/W-0h
Table 34-108 XCERG Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERGR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.31 XCERH Register (Offset = 1Eh) [Reset = 0000h]

XCERH is shown in Figure 34-97 and described in Table 34-109.

Return to the Summary Table.

XCERH contains the transmit channel enable registers for the H partition. This register is only used when the transmitter is configured to allow individual disabling/enabling and masking/unmasking of the channels (e.g. XMCM is nonzero).

Figure 34-97 XCERH Register
15141312111098
XCERH
R/W-0h
76543210
XCERH
R/W-0h
Table 34-109 XCERH Register Field Descriptions
BitFieldTypeResetDescription
15-0XCERHR/W0hTransmit channel enable bit.
The role of this bit depends on which transmit multichannel selection mode is selected with the XMCM bits.

Reset type: SYSRSn


0h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Disable and mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Mask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding receive channel enable bit, this channel's data cannot appear on the DX pin.
1h (R/W) = For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
Enable and unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
Unmask the channel that is mapped to XCEx.

For multichannel selection when XMCM = 11b
(all channels masked unless selected):
Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur.

34.16.2.32 MFFINT Register (Offset = 23h) [Reset = 0000h]

MFFINT is shown in Figure 34-98 and described in Table 34-110.

Return to the Summary Table.

MFFINT contains the enable bits for both the transmitter and receiver interupts.

Figure 34-98 MFFINT Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDRINTRESERVEDXINT
R-0hR/W-0hR-0hR/W-0h
Table 34-110 MFFINT Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0hReserved
2RINTR/W0hEnable for Receive Interrupt

Reset type: SYSRSn


0h (R/W) = Receive interrupt on RRDY is disabled.
1h (R/W) = Receive interrupt on RRDY is enabled.
1RESERVEDR0hReserved
0XINTR/W0hEnable for Transmit Interrupt

Reset type: SYSRSn


0h (R/W) = Transmit interrupt on XRDY is disabled.
1h (R/W) = Transmit interrupt on XRDY is enabled.