30V, 2A double ended 1MHz PWM controller with 9.2V/8.4V UVLO and 100% duty cycle, 0C to 70C


Product details


Topology Boost, Buck, Flyback, Forward Control method Current, Voltage VCC (Min) (V) 9.2 VCC (Max) (V) 22 Duty cycle (Max) (%) 100 UVLO thresholds on/off (V) 9.2/8.4 Frequency (Max) (kHz) 1000 Operating temperature range (C) 0 to 70 Gate drive (Typ) (A) 2 Features Error Amplifier, Leading Edge Blanking, Multi-topology, Soft Start, Synchronization Pin Rating Catalog open-in-new Find other PWM controllers & resonant controllers

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (DW) 16 77 mm² 10.3 x 7.5 open-in-new Find other PWM controllers & resonant controllers


  • Improved Versions of the UC3823/UC3825 PWMs
  • Compatible with Voltage-Mode or Current-Mode Control Methods
  • Practical Operation at Switching Frequencies to 1 MHz
  • 50-ns Propagation Delay to Output
  • High-Current Dual Totem Pole Outputs (2-A Peak)
  • Trimmed Oscillator Discharge Current
  • Low 100-µA Startup Current
  • Pulse-by-Pulse Current Limiting Comparator
  • Latched Overcurrent Comparator With Full Cycle Restart

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The UC3823A and UC3823B and the UC3825A and UC3825B family of PWM controllers are improved versions of the standard UC3823 and UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2-A peak currents during transitions.

Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.

The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. "A" version parts have UVLO thresholds identical to the original UC3823 and UC3825. The "B" versions have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.

Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for detailed technical and applications information.

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Technical documentation

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Type Title Date
* Datasheet UC2823x, UC2825x, UC3823x, UC3825x: High Speed PWM Controller datasheet (Rev. E) Sep. 09, 2010
Selection guides Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Application notes U-128 The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers Sep. 05, 1999
Application notes U-160 Simple Circuit Modifications Enhance Optocoupler Performance Sep. 05, 1999

Design & development

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CAD/CAE symbols

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PDIP (N) 16 View options
SOIC (DW) 16 View options

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