設計工具
DS250DF210-DESIGN — DS250DF210 design files
DS250DF210 design files include SigCon Architect profile, EVM files, IBIS-AMI model, Programmer's Guide, and several application notes.
DS250DF210
- Dual-channel multi-rate retimer with integrated signal conditioning
- All channels lock independently from 20.6 to 25.8 Gbps (including sub-rates such as 10.3125 Gbps, 12.5 Gbps, and more)
- Ultra-low latency: <500 ps Typical for 25.78125-Gbps data rate
- Single power supply, no low-jitter reference clock required, and minimal supply decoupling to reduce board routing complexity and BOM cost
- Adaptive Continuous Time Linear Equalizer (CTLE)
- Adaptive Decision Feedback Equalizer (DFE)
- Integrated 2 x 2 cross point
- Low-jitter transmitter with 3-Tap FIR filter
- Combined equalization supporting 35+ dB channel loss at 12.9 GHz
- Adjustable transmit amplitude: 205 mVppd to 1225 mVppd (typical)
- On-Chip Eye Opening Monitor (EOM), PRBS pattern checker and generator
- Small 6-mm × 6-mm BGA package with easy flow-through routing
The DS250DF210 device is a two-channel, multi-rate retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired, high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.
Each channel of the DS250DF210 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF210 to support individual lane Forward Error Correction (FEC) pass-through.
The DS250DF210 has a single power supply and minimal need for external components. These features reduce PCB-routing complexity and BOM cost.
The advanced equalization features of the DS250DF210 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF210 implements a 2x2 cross-point, providing the host with lane crossing, fanout, and multiplexing options
The DS250DF210 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM using Common Channel format. A non-disruptive, on-chip eye monitor and a PRBS generator or checker allow for in-system diagnostics.
索取更多資訊
提供 IBIS AMI 模型、裝置編程指南和裝置 GUI 設定檔： 立即索取
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS250DF210 25-Gbps Multi-Rate 2-Channel Retimer datasheet (Rev. B) | PDF | HTML | 2019年 10月 24日 |
| Application note | Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. B) | PDF | HTML | 2023年 5月 1日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
DS250DF410EVM — DS250DF410 25 Gbps 多速率四通道重定時器評估模組
DS250DF410EVM 可輕鬆評估 25Gbps 重定時器 DS250DF410。使用者需要透過 Huber+Suhner 1x8 MXP 連接器，為 EVM 提供電源和高速流量。不包含 Huber+Suhner 纜線。
使用者可以透過板載 USB2ANY 連線及 EVM 軟體來評估裝置功能，例如訊號偵測、等化設定、Tx 輸出設定、EEPROM 檔案產生及其他暫存器功能。
使用指南: PDF
設計工具
DS250DF410-DESIGN — DS250DF410 Multi-Rate 4-Channel Retimer Design Files
支援產品和硬體
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ABM) | 101 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。