DS90C363B
- No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered.
- Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or −5% down spread.
- "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high.
- 18 to 68 MHz shift clock support
- Best–in–Class Set & Hold Times on TxINPUTs
- Tx power consumption < 130 mW (typ) at 65MHz Grayscale
- 40% Less Power Dissipation than BiCMOS Alternatives
- Tx Power-down mode < 37μW (typ)
- Supports VGA, SVGA, XGA and Dual Pixel SXGA.
- Narrow bus reduces cable size and cost
- Up to 1.3 Gbps throughput
- Up to 170 Megabytes/sec bandwidth
- 345 mV (typ) swing LVDS devices for low EMI
- PLL requires no external components
- Compatible with TIA/EIA-644 LVDS standard
- Low profile 48-lead TSSOP package
- Improved replacement for:
- SN75LVDS84, DS90C363A
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.
The DS90C363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90C363B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | DS90C363B 3.3V Prog LVDS Transm 18-Bit FPD Link -65 MHz datasheet (Rev. F) | 2013年 4月 12日 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018年 6月 29日 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017年 8月 8日 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 2016年 1月 13日 | ||
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004年 5月 15日 | ||
| Application note | AN-1056 STN Application Using FPD-Link | 2004年 5月 14日 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004年 5月 14日 |
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