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ISO5852S

現行

具有分離輸出、STO 和保護功能的 5.7kVrms、2.5A/5A 單通道絕緣式閘極驅動器

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產品規格表

ISO5852S

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Isolation rating Reinforced Power switch IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 1500 Transient isolation voltage (VIOTM) (VPK) 8000 Peak output current (A) 5 Peak output current (source) (typ) (A) 2.5 Peak output current (sink) (typ) (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (min) (V) 15 Output VCC/VDD (max) (V) 30 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
Number of channels 1 Isolation rating Reinforced Power switch IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 1500 Transient isolation voltage (VIOTM) (VPK) 8000 Peak output current (A) 5 Peak output current (source) (typ) (A) 2.5 Peak output current (sink) (typ) (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (min) (V) 15 Output VCC/VDD (max) (V) 30 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.
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類型 標題 日期
* Data sheet ISO5852S High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet (Rev. C) PDF | HTML 2023年 5月 30日
Certificate VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. Z) 2026年 1月 8日
Certificate UL Certificate of Compliance File E181974 Vol 4 Sec 6 (Rev. R) 2025年 9月 8日
Certificate TUV Certificate for Isolation Devices (Rev. L) 2025年 8月 15日
Application brief Does My Design Need a Miller Clamp? PDF | HTML 2024年 12月 11日
Application note Choosing Appropriate Protection Approach for IGBT and SiC Power Modules PDF | HTML 2024年 7月 19日
Application note Digital Isolator Design Guide (Rev. G) PDF | HTML 2023年 9月 13日
User guide UCC217xx and ISO5x5x Half-Bridge EVM User's Guide for Wolfspeed 1200-V SiC 2023年 9月 1日
White paper Circuit Board Insulation Design According to IEC60664 for Motor Drive Apps PDF | HTML 2023年 8月 31日
Certificate ISO5451 CQC Certificate of Product Certification 2023年 8月 16日
Application note Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting (Rev. A) PDF | HTML 2022年 2月 17日
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 2021年 12月 16日
Certificate CSA Certification (Rev. Q) 2021年 6月 14日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Functional safety information Isolation in AC Motor Drives: Understanding the IEC 61800-5-1 Safety Standard (Rev. A) 2019年 9月 19日
Technical article Designing highly efficient, powerful and fast EV charging stations PDF | HTML 2019年 8月 6日
Analog Design Journal Pushing the envelope with high-performance digital-isolation technology (Rev. A) 2018年 8月 22日
EVM User's guide ISO5852SDW Driving and Protecting SiC and IGBT Power Modules 2018年 5月 24日
Functional safety information Isolation in solar power converters: Understanding the IEC62109-1 safety standar (Rev. A) 2018年 5月 18日
Technical article Why capacitive isolation: a vital building block for sensors in smart cities PDF | HTML 2018年 1月 16日
Application note Isolation Glossary (Rev. A) 2017年 9月 19日
Technical article Understanding isolator failure modes for safe isolation PDF | HTML 2016年 3月 28日
Technical article 7 steps to choose the right isolators for AC motor-drive applications PDF | HTML 2015年 11月 24日
Analog Design Journal 4Q 2015 Analog Applications Journal 2015年 10月 30日
Analog Design Journal Common-mode transient immunity for isolated gate drivers 2015年 10月 30日
White paper Understanding electromagnetic compliance tests in digital isolators 2014年 10月 17日
White paper High-voltage reinforced isolation: Definitions and test methodologies 2014年 10月 16日
Application note Shelf-Life Evaluation of Lead-Free Component Finishes 2004年 5月 24日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ISO5852SDWEVM-017 — 適用於 SiC 和 IGBT 電源模組的驅動和保護評估板

ISO5852SDWEVM-017 是一款精巧的雙通道隔離閘極驅動板，為標準 62-mm 封裝的半橋 Sic MOSFET 和 IGBT 功率模組提供所需的驅動、偏壓、保護和診斷功能。此 TI EVM 是以 SOIC-16DW 封裝，沿面距離與電氣間隙為 8.0mm 的 5.7 kVrms 強化型隔離驅動器 IC ISO5852SDW 為基礎。EVM 包括 SN6505B 架構的隔離式偏壓電源供應器，以及由放大器 AMC1401 隔離的溫度與匯流排電壓監控。

使用指南: PDF
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開發板

ISO5852SEVM — 強化型隔離式 IGBT 閘極驅動器評估模組

This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.

使用指南: PDF
TI.com 無法提供
模擬型號

ISO5852S IBIS Model

SLLM283.ZIP (33 KB) - IBIS Model
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模擬型號

ISO5852S PSpice Transient Model (Rev. A)

SLLM300A.ZIP (232 KB) - PSpice Model
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模擬型號

ISO5852S TINA-TI Reference Design

SLLM436.TSC (1537 KB) - TINA-TI Reference Design
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模擬型號

ISO5852S TINA-TI SPICE Model

SLLM435.ZIP (31 KB) - TINA-TI Spice Model
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模擬型號

ISO5852S Unencrypted PSPICE Transient Model

SLLM446.ZIP (4 KB) - PSpice Model
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設計工具

SLLR117 — ISO5852SDWEVM-017 Design Files

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產品
隔離式閘極驅動器
  • ISO5852S — 具有分離輸出、STO 和保護功能的 5.7kVrms、2.5A/5A 單通道絕緣式閘極驅動器
硬體開發
開發板
  • ISO5852SDWEVM-017 — 適用於 SiC 和 IGBT 電源模組的驅動和保護評估板
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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參考設計

TIDA-00195 — 適用於 3 相逆變器系統的絕緣式 IGBT 閘極驅動器評估平台參考設計

The TIDA-00195 reference design consists of a 22kW power stage with TI’s new reinforced isolated IGBT gate driver ISO5852S intended for motor control in various applications. This design allows performance evaluation of the ISO5852S in 3-phase inverter incorporating 1200V rated IGBT modules (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01599 — TÜV SÜD 評估工業驅動器的安全扭矩關閉 (STO) 參考設計 (IEC 61800-5-2)

本參考設計概述具有 CMOS 輸入隔離式 IGBT 閘極驅動器的三相逆變器的安全扭矩關閉 (STO) 子系統。STO 子系統採用雙通道架構 (1oo2)，硬體容錯範圍爲 1 (HFT=1)。實作時遵循去能脫扣概念。當雙 STO 輸入 (STO_1 和 STO_2) 變低電位作動時，六個隔離 IGBT 柵極驅動器的一次和二次側對應電源供電將透過負載開關切斷。如此可消除控制馬達並為馬達通電的可能性。STO 參考設計 (1oo2) 已由 TÜV SÜD 進行評估，一般適用於 SIL 3 和 PL e/Cat。3.
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00917 — 適用於具有短路保護功能和電流緩衝器的並聯 IGBT 的閘極驅動器參考設計

輸出功率額定值較高的電源轉換設備需要並聯絕緣柵雙極電晶體 (IGBT)，因為單一 IGBT 無法提供所需的負載電流。此參考設計實作強化隔離式 IGBT 閘極控制模組，以半橋配置驅動並聯 IGBT。並聯 IGBT 會在閘極驅動器（驅動強度不足）和系統層級帶來挑戰，需在兩個 IGBT 維持相等的電流分配，同時確保快速導通和關閉。此參考設計使用強化隔離式 IGBT 閘極驅動器，並具備去飽和偵測與軟關閉等整合式功能，以在發生故障時保護 IGBT。透過外部 BJT 電流升壓級獲得更高的閘極驅動電流 (15A)，無需犧牲軟關閉功能。此外，此設計展示了在並聯操作 IGBT 時避免閘極電流迴路的機制。
Design guide: PDF
電路圖: PDF
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