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PCA9306H

現行

2 位元雙向 400-kHz I2C/SMBus 電壓電平轉換器

PCA9306H

現行

產品詳細資料

Operating temperature range (°C) to
Operating temperature range (°C) to
  • 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C Applications
  • I2C and SMBus compatible
  • Less than 1.5ns maximum propagation delay to accommodate standard-mode and fast-mode I2C devices and multiple controllers
  • Negative glitch immunity on the I2C lines when EN = 0V
  • Allows voltage-level translation between
    • 1.2V VREF1 and 1.8V, 2.5V, 3.3V, or 5V VREF2
    • 1.8V VREF1 and 2.5V, 3.3V, or 5V VREF2
    • 2.5V VREF1 and 3.3V or 5V VREF2
    • 3.3V VREF1 and 5V VREF2
  • Provides bidirectional voltage translation with no direction pin
  • Low 3.5Ω ON-state resistance between input and output ports provides less signal distortion
  • Open-drain I2C I/O ports (SCL1, SDA1, SCL2, and SDA2)
  • 5V Tolerant I2C I/O ports to support mixed-mode signal operation
  • High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = low
  • Lockup-free operation for isolation when EN = low
  • Flow-through pinout for ease of printed-circuit-board trace routing
  • Latch-up performance exceeds 100mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V Human-body model (A114-A)
    • 1000V Charged-device model (C101)
  • 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C Applications
  • I2C and SMBus compatible
  • Less than 1.5ns maximum propagation delay to accommodate standard-mode and fast-mode I2C devices and multiple controllers
  • Negative glitch immunity on the I2C lines when EN = 0V
  • Allows voltage-level translation between
    • 1.2V VREF1 and 1.8V, 2.5V, 3.3V, or 5V VREF2
    • 1.8V VREF1 and 2.5V, 3.3V, or 5V VREF2
    • 2.5V VREF1 and 3.3V or 5V VREF2
    • 3.3V VREF1 and 5V VREF2
  • Provides bidirectional voltage translation with no direction pin
  • Low 3.5Ω ON-state resistance between input and output ports provides less signal distortion
  • Open-drain I2C I/O ports (SCL1, SDA1, SCL2, and SDA2)
  • 5V Tolerant I2C I/O ports to support mixed-mode signal operation
  • High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = low
  • Lockup-free operation for isolation when EN = low
  • Flow-through pinout for ease of printed-circuit-board trace routing
  • Latch-up performance exceeds 100mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V Human-body model (A114-A)
    • 1000V Charged-device model (C101)

The PCA9306H device is a dual bidirectional I2C and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.2V to 3.3V VREF1 and 1.8V to 5.5V VREF2.

The PCA9306H device allows bidirectional voltage translations between 1.2V and 5V, without the use of a direction pin. The low ON-state resistance (RON) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.

In addition to voltage translation, the PCA9306H device can be used to separate a 400kHz bus from a 100kHz bus by controlling the EN pin to disconnect the slower bus during fast-mode communication.

The PCA9306H device is a dual bidirectional I2C and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.2V to 3.3V VREF1 and 1.8V to 5.5V VREF2.

The PCA9306H device allows bidirectional voltage translations between 1.2V and 5V, without the use of a direction pin. The low ON-state resistance (RON) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.

In addition to voltage translation, the PCA9306H device can be used to separate a 400kHz bus from a 100kHz bus by controlling the EN pin to disconnect the slower bus during fast-mode communication.

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重要文件 類型 標題 格式選項 日期
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Programming Fun Lights With TI's TCA6507 2007年 11月 30日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

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