SN65CML100

現行

1.5-Gbps LVDS/LVPECL/CML 至 CML 轉譯器/中繼器

產品詳細資料

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 3
類型 標題 日期
* Data sheet 1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater datasheet 2002年 11月 11日
Application note Signaling Rate vs. Distance for Differential Buffers 2010年 1月 26日
EVM User's guide 2-GBPS Differential Repeater EVM (Rev. A) 2002年 11月 11日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

SN65CML100EVM — SN65CML100 評估模組

The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)

使用指南: PDF
TI.com 無法提供
模擬型號

SN65CML100 IBIS Model

SLLC131.ZIP (3 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片