SPRSPB9B July   2025  – October 2025 F28E120SB , F28E120SC

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and PWM X-BAR
      6. 5.4.6 GPIO and ADC Allocation
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - Internal Supply
      2. 6.4.2 Operating Mode Test Description
      3. 6.4.3 Current Consumption Graphs
      4. 6.4.4 Reducing Current Consumption
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PT Package
    7. 6.7  Thermal Resistance Characteristics for VFC Package
    8. 6.8  Thermal Resistance Characteristics for RHB Package
    9. 6.9  Thermal Design Considerations
    10. 6.10 System
      1. 6.10.1  Power Management Module (PMM)
        1. 6.10.1.1 Introduction
        2. 6.10.1.2 Overview
          1. 6.10.1.2.1 Power Rail Monitors
            1. 6.10.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.10.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
          2. 6.10.1.2.2 External Supervisor Usage
          3. 6.10.1.2.3 Delay Blocks
        3. 6.10.1.3 External Components
          1. 6.10.1.3.1 Decoupling Capacitors
            1. 6.10.1.3.1.1 VDDIO Decoupling
        4. 6.10.1.4 Power Sequencing
          1. 6.10.1.4.1 Supply Pins Ganging
          2. 6.10.1.4.2 Signal Pins Power Sequence
          3. 6.10.1.4.3 Supply Pins Power Sequence
            1. 6.10.1.4.3.1 Internal Power-Up Sequence
            2. 6.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.10.1.4.3.3 Supply Slew Rate
        5. 6.10.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.10.1.6 Power Management Module Electrical Data and Timing
          1. 6.10.1.6.1 Power Management Module Operating Conditions
          2. 6.10.1.6.2 Power Management Module Characteristics
      2. 6.10.2  Reset Timing
        1. 6.10.2.1 Reset Sources
        2. 6.10.2.2 Reset Electrical Data and Timing
          1. 6.10.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.10.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.10.2.2.3 Reset Timing Diagrams
      3. 6.10.3  Clock Specifications
        1. 6.10.3.1 Clock Sources
        2. 6.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.10.3.2.1.1 Input Clock Frequency
            2. 6.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.10.3.2.1.3 X1 Timing Requirements
            4. 6.10.3.2.1.4 PLL Characteristics
            5. 6.10.3.2.1.5 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            6. 6.10.3.2.1.6 Internal Clock Frequencies
        3. 6.10.3.3 Input Clocks and PLLs
        4. 6.10.3.4 XTAL Oscillator
          1. 6.10.3.4.1 Introduction
          2. 6.10.3.4.2 Overview
            1. 6.10.3.4.2.1 Electrical Oscillator
              1. 6.10.3.4.2.1.1 Modes of Operation
                1. 6.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.10.3.4.2.2 Quartz Crystal
          3. 6.10.3.4.3 Functional Operation
            1. 6.10.3.4.3.1 ESR – Effective Series Resistance
            2. 6.10.3.4.3.2 Rneg – Negative Resistance
            3. 6.10.3.4.3.3 Start-up Time
              1. 6.10.3.4.3.3.1 X1/X2 Precondition
            4. 6.10.3.4.3.4 DL – Drive Level
          4. 6.10.3.4.4 How to Choose a Crystal
          5. 6.10.3.4.5 Testing
          6. 6.10.3.4.6 Common Problems and Debug Tips
          7. 6.10.3.4.7 Crystal Oscillator Specifications
            1. 6.10.3.4.7.1 Crystal Oscillator Parameters
            2. 6.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.10.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.10.3.5 Internal Oscillators
          1. 6.10.3.5.1 System Oscillator SYSOSC
          2. 6.10.3.5.2 Wide Range Oscillator WROSC
      4. 6.10.4  Flash Parameters
        1. 6.10.4.1 Flash Parameters 
      5. 6.10.5  RAM Specifications
      6. 6.10.6  ROM Specifications
      7. 6.10.7  Emulation/JTAG
        1. 6.10.7.1 JTAG Electrical Data and Timing
          1. 6.10.7.1.1 JTAG Timing Requirements
          2. 6.10.7.1.2 JTAG Switching Characteristics
          3. 6.10.7.1.3 JTAG Timing Diagram
        2. 6.10.7.2 cJTAG Electrical Data and Timing
          1. 6.10.7.2.1 cJTAG Timing Requirements
          2. 6.10.7.2.2 cJTAG Switching Characteristics
          3. 6.10.7.2.3 cJTAG Timing Diagram
      8. 6.10.8  GPIO Electrical Data and Timing
        1. 6.10.8.1 GPIO – Output Timing
          1. 6.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.10.8.1.2 General-Purpose Output Timing Diagram
        2. 6.10.8.2 GPIO – Input Timing
          1. 6.10.8.2.1 General-Purpose Input Timing Requirements
          2. 6.10.8.2.2 Sampling Mode
        3. 6.10.8.3 Sampling Window Width for Input Signals
      9. 6.10.9  Interrupts
        1. 6.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.10.9.1.1 External Interrupt Timing Requirements
          2. 6.10.9.1.2 External Interrupt Switching Characteristics
          3. 6.10.9.1.3 External Interrupt Timing
      10. 6.10.10 Low-Power Modes
        1. 6.10.10.1 Clock-Gating Low-Power Modes
        2. 6.10.10.2 Low-Power Mode Wake-up Timing
          1. 6.10.10.2.1 IDLE Mode Timing Requirements
          2. 6.10.10.2.2 IDLE Mode Switching Characteristics
          3. 6.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.10.10.2.4 STANDBY Mode Timing Requirements
          5. 6.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.10.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.10.10.2.7 HALT Mode Timing Requirements
          8. 6.10.10.2.8 HALT Mode Switching Characteristics
          9. 6.10.10.2.9 HALT Entry and Exit Timing Diagram
    11. 6.11 Analog Peripherals
      1. 6.11.1 Analog Pins and Internal Connections
      2. 6.11.2 Analog-to-Digital Converter (ADC)
        1. 6.11.2.1 ADC Configurability
          1. 6.11.2.1.1 Signal Mode
        2. 6.11.2.2 ADC Electrical Data and Timing
          1. 6.11.2.2.1 ADC Operating Conditions
          2. 6.11.2.2.2 ADC Characteristics
          3. 6.11.2.2.3 ADC INL and DNL
          4. 6.11.2.2.4 ADC Performance Per Pin
          5. 6.11.2.2.5 ADC Input Model
          6. 6.11.2.2.6 ADC Timing Diagrams
      3. 6.11.3 Comparator Subsystem (CMPSS_LITE)
        1. 6.11.3.1 COMPDACOUT
        2. 6.11.3.2 CMPSS Connectivity Diagram
        3. 6.11.3.3 Block Diagram
        4. 6.11.3.4 CMPSS Electrical Data and Timing
          1. 6.11.3.4.1 CMPSS_LITE Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.11.3.4.2 CMPSS_LITE DAC Static Electrical Characteristics
          4. 6.11.3.4.3 CMPSS Illustrative Graphs
          5. 6.11.3.4.4 Buffered Output from CMPx_LITE_DACL Operating Conditions
          6. 6.11.3.4.5 Buffered Output from CMPx_LITE_DACL Electrical Characteristics
      4. 6.11.4 Programmable Gain Amplifier (PGA)
        1. 6.11.4.1 PGA Electrical Data and Timing
          1. 6.11.4.1.1 PGA Operating Conditions
          2. 6.11.4.1.2 PGA Characteristics
      5. 6.11.5 Temperature Sensor
        1. 6.11.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.11.5.1.1 Temperature Sensor Characteristics
    12. 6.12 Control Peripherals
      1. 6.12.1 Multichannel Pulse Width Modulator (MCPWM)
        1. 6.12.1.1 Control Peripherals Synchronization
        2. 6.12.1.2 MCPWM Electrical Data and Timing
          1. 6.12.1.2.1 MCPWM Timing Requirements
          2. 6.12.1.2.2 MCPWM Switching Characteristics
          3. 6.12.1.2.3 Trip-Zone Input Timing
            1. 6.12.1.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      2. 6.12.2 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.12.2.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.12.2.2 ADCSOCAO or ADCSOCBO Timing Diagram
      3. 6.12.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.12.3.1 eQEP Electrical Data and Timing
          1. 6.12.3.1.1 eQEP Timing Requirements
          2. 6.12.3.1.2 eQEP Switching Characteristics
      4. 6.12.4 Enhanced Capture (eCAP)
        1. 6.12.4.1 eCAP Block Diagram
        2. 6.12.4.2 eCAP Synchronization
        3. 6.12.4.3 eCAP Electrical Data and Timing
          1. 6.12.4.3.1 eCAP Switching Characteristics
    13. 6.13 Communications Peripherals
      1. 6.13.1 Inter-Integrated Circuit (I2C)
        1. 6.13.1.1 I2C Electrical Data and Timing
          1. 6.13.1.1.1 I2C Timing Requirements
          2. 6.13.1.1.2 I2C Switching Characteristics
          3. 6.13.1.1.3 I2C Timing Diagram
      2. 6.13.2 Universal Asynchronous Receiver-Transmitter (UART)
      3. 6.13.3 Serial Peripheral Interface (SPI)
        1. 6.13.3.1 SPI Controller Mode Timings
          1. 6.13.3.1.1 SPI Controller Mode Timing Requirements
          2. 6.13.3.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.13.3.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.13.3.1.4 SPI Controller Mode Timing Diagrams
        2. 6.13.3.2 SPI Peripheral Mode Timings
          1. 6.13.3.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.13.3.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.13.3.2.3 SPI Peripheral Mode Timing Diagrams
      4. 6.13.4 Serial Communications Interface (SCI)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Memory
      1. 7.2.1 C28x Memory Map
        1. 7.2.1.1 Dedicated RAM (Mx RAM)
      2. 7.2.2 Flash Memory Map
      3. 7.2.3 Peripheral Registers Memory Map
    3. 7.3  Identification
    4. 7.4  C28x Processor
      1. 7.4.1 Floating-Point Unit (FPU)
    5. 7.5  Direct Memory Access (DMA)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
  • PT|48
  • VFC|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAME MUX POSITION 48 PT 32 VFC 32 RHB PIN TYPE DESCRIPTION
ANALOG
A0 11 7 7 I ADC-A Input 0
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
PGA1_INM2 I PGA-1 Minus 2
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A1 10 7 7 I ADC-A Input 1
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
A2 6 4 4 I ADC-A Input 2
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
GPIO224 I/O General-Purpose Input Output 224 This pin also has digital mux functions which are described in the GPIO section of this table.
A3 5 3 3 I ADC-A Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
GPIO242 I/O General-Purpose Input Output 242 This pin also has digital mux functions which are described in the GPIO section of this table.
A4 19 12 12 I ADC-A Input 4
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
PGA1_INM1 I PGA-1 Minus 1
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
A5 9 6 6 I ADC-A Input 5
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244
A6 4 2 2 I ADC-A Input 6
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
GPIO228 I/O General-Purpose Input Output 228 This pin also has digital mux functions which are described in the GPIO section of this table.
A7 15 8 8 I ADC-A Input 7
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245
A8 16 9 9 I ADC-A Input 8
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4
PGA1_OUT O PGA-1 Output
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
A9 20 13 13 I ADC-A Input 9
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
GPIO227 I/O General-Purpose Input Output 227 This pin also has digital mux functions which are described in the GPIO section of this table.
A10 21 13 13 I ADC-A Input 10
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
GPIO230 I/O General-Purpose Input Output 230 This pin also has digital mux functions which are described in the GPIO section of this table.
A11 8 6 6 I ADC-A Input 11
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
PGA1_INP1 I PGA-1 Plus 1
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
A12 14 8 8 I ADC-A Input 12
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
A14 7 5 5 I ADC-A Input 14
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
A15 7 5 5 I ADC-A Input 15
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
A16 2 32 32 I ADC-A Input 16
GPIO28 I/O General-Purpose Input Output 28 This pin also has digital mux functions which are described in the GPIO section of this table.
PGA1_INP2 I PGA-1 Plus 2
A19 23 I ADC-A Input 19
GPIO13 I/O General-Purpose Input Output 13 This pin also has digital mux functions which are described in the GPIO section of this table.
A20 24 I ADC-A Input 20
GPIO12 I/O General-Purpose Input Output 12 This pin also has digital mux functions which are described in the GPIO section of this table.
CMP3_HP0 4 2 2 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
GPIO226 I/O General-Purpose Input Output 226 This pin also has digital mux functions which are described in the GPIO section of this table.
PGA1_INP3 I PGA-1 Plus 3
VREFHI 12 11 11 I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor and a 10Ohm resistor in series on this pin. This capacitor and resistor should be placed as close to the device as possible between the VREFHI and VREFLO pins. On the 32 QFN package, VREFHI is internally tied to VDDA.
VREFLO 13 10 10 I ADC Low Reference, should be tied to VSSA
GPIO
GPIO0 0, 4, 8, 12 42 28 28 I/O General-Purpose Input Output 0
MCPWM1_1A 1 O MCPWM-1 Output 1A
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
EQEP1_INDEX 13 I/O eQEP-1 Index
MCPWM1_3A 15 O MCPWM-1 Output 3A
GPIO1 0, 4, 8, 12 41 27 27 I/O General-Purpose Input Output 1
MCPWM1_1B 1 O MCPWM-1 Output 1B
OUTPUTXBAR4 3 O Output X-BAR Output 4
SCIA_TX 5 O SCI-A Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP1_STROBE 9 I/O eQEP-1 Strobe
MCPWM1_3B 15 O MCPWM-1 Output 3B
GPIO2 0, 4, 8, 12 40 I/O General-Purpose Input Output 2
MCPWM1_2A 1 O MCPWM-1 Output 2A
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
SCIA_TX 9 O SCI-A Transmit Data
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
GPIO3 0, 4, 8, 12 39 26 26 I/O General-Purpose Input Output 3
MCPWM1_2B 1 O MCPWM-1 Output 2B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 I SCI-A Receive Data
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO4 0, 4, 8, 12 38 25 25 I/O General-Purpose Input Output 4
MCPWM1_3A 1 O MCPWM-1 Output 3A
I2CA_SCL 2 I/OD I2C-A Open-Drain Bidirectional Clock
OUTPUTXBAR3 5 O Output X-BAR Output 3
EQEP1_STROBE 9 I/O eQEP-1 Strobe
SPIA_POCI 14 I/O SPI-A Peripheral Out, Controller In (POCI)
MCPWM1_1A 15 O MCPWM-1 Output 1A
GPIO5 0, 4, 8, 12 47 30 30 I/O General-Purpose Input Output 5
MCPWM1_3B 1 O MCPWM-1 Output 3B
I2CA_SDA 2 I/OD I2C-A Open-Drain Bidirectional Data
OUTPUTXBAR3 3 O Output X-BAR Output 3
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
SPIA_POCI 9 I/O SPI-A Peripheral Out, Controller In (POCI)
SCIA_RX 11 I SCI-A Receive Data
MCPWM1_1B 15 O MCPWM-1 Output 1B
GPIO6 0, 4, 8, 12 48 I/O General-Purpose Input Output 6
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External MCPWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
MCPWM1_3A 10 O MCPWM-1 Output 3A
MCPWM1_2A 15 O MCPWM-1 Output 2A
GPIO7 0, 4, 8, 12 43 29 I/O General-Purpose Input Output 7
MCPWM1_2A 2 O MCPWM-1 Output 2A
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
MCPWM3_1A 9 O MCPWM-3 Output 1A
SCIA_TX 11 O SCI-A Transmit Data
MCPWM1_2B 15 O MCPWM-1 Output 2B
GPIO8 0, 4, 8, 12 I/O General-Purpose Input Output 8
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO9 0, 4, 8, 12 I/O General-Purpose Input Output 9
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 I/O SPI-A Clock
MCPWM1_1B 9 O MCPWM-1 Output 1B
I2CA_SCL 14 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO10 0, 4, 8, 12 I/O General-Purpose Input Output 10
MCPWM1_2B 2 O MCPWM-1 Output 2B
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
GPIO11 0, 4, 8, 12 14 14 I/O General-Purpose Input Output 11
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
MCPWM3_1B 9 O MCPWM-3 Output 1B
EQEP1_A 11 I eQEP-1 Input A
SPIA_PICO 13 I/O SPI-A Peripheral In, Controller Out (PICO)
GPIO12 0, 4, 8, 12 24 I/O General-Purpose Input Output 12 This pin also has analog functions which are described in the ANALOG section of this table.
MCPWM3_1A 1 O MCPWM-3 Output 1A
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
SPIA_CLK 11 I/O SPI-A Clock
GPIO13 0, 4, 8, 12 23 I/O General-Purpose Input Output 13 This pin also has analog functions which are described in the ANALOG section of this table.
MCPWM3_1B 1 O MCPWM-3 Output 1B
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
SPIA_POCI 11 I/O SPI-A Peripheral Out, Controller In (POCI)
GPIO16 0, 4, 8, 12 26 I/O General-Purpose Input Output 16
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 I/O eQEP-1 Strobe
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
EQEP1_B 13 I eQEP-1 Input B
GPIO17 0, 4, 8, 12 I/O General-Purpose Input Output 17
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EQEP1_INDEX 9 I/O eQEP-1 Index
GPIO18 0, 4, 8, 12 33 21 21 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_A 9 I eQEP-1 Input A
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
X2 ALT I/O Crystal oscillator output.
GPIO19 0, 4, 8, 12 34 22 22 I/O General-Purpose Input Output 19
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
SCIB_RX 2 I SCI-B Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_B 9 I eQEP-1 Input B
X1 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock.
GPIO20 0, 4, 8, 12 I/O General-Purpose Input Output 20
EQEP1_A 1 I eQEP-1 Input A
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
UARTA_TX 15 O UART-A Transmit Data
GPIO21 0, 4, 8, 12 I/O General-Purpose Input Output 21
EQEP1_B 1 I eQEP-1 Input B
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
UARTA_RX 15 I UART-A Receive Data
GPIO22 0, 4, 8, 12 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
GPIO23 0, 4, 8, 12 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SPIA_PTE 2 I/O SPI-A Peripheral Transmit Enable (PTE)
SCIB_RX 3 I SCI-B Receive Data
GPIO24 0, 4, 8, 12 27 15 15 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP1_A 2 I eQEP-1 Input A
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
GPIO28 0, 4, 8, 12 2 32 32 I/O General-Purpose Input Output 28 This pin also has analog functions which are described in the ANALOG section of this table.
SCIA_RX 1 I SCI-A Receive Data
OUTPUTXBAR8 2 O Output X-BAR Output 8
MCPWM3_1A 3 O MCPWM-3 Output 1A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
EQEP1_STROBE 9 I/O eQEP-1 Strobe
UARTA_TX 10 O UART-A Transmit Data
SPIA_CLK 11 I/O SPI-A Clock
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CA_SDA 14 I/OD I2C-A Open-Drain Bidirectional Data
GPIO29 0, 4, 8, 12 1 31 31 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
MCPWM1_2A 2 O MCPWM-1 Output 2A
MCPWM3_1B 3 O MCPWM-3 Output 1B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
EQEP1_INDEX 9 I/O eQEP-1 Index
UARTA_RX 10 I UART-A Receive Data
SPIA_PTE 11 I/O SPI-A Peripheral Transmit Enable (PTE)
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CA_SCL 14 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO30 0, 4, 8, 12 I/O General-Purpose Input Output 30
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP1_STROBE 6 I/O eQEP-1 Strobe
MCPWM1_1A 11 O MCPWM-1 Output 1A
GPIO32 0, 4, 8, 12 32 20 20 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_INDEX 2 I/O eQEP-1 Index
SPIA_CLK 3 I/O SPI-A Clock
UARTA_RX 6 I UART-A Receive Data
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
GPIO33 0, 4, 8, 12 25 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
OUTPUTXBAR4 5 O Output X-BAR Output 4
UARTA_TX 6 O UART-A Transmit Data
EQEP1_B 11 I eQEP-1 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
GPIO35 0, 4, 8, 12 31 19 19 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
SPIA_POCI 2 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
UARTA_RX 7 I UART-A Receive Data
EQEP1_A 9 I eQEP-1 Input A
TDI 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 29 17 17 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
SPIA_PTE 2 I/O SPI-A Peripheral Transmit Enable (PTE)
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
UARTA_TX 7 O UART-A Transmit Data
EQEP1_B 9 I eQEP-1 Input B
SYNCOUT 13 O External MCPWM Synchronization Pulse
TDO 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO39 0, 4, 8, 12 I/O General-Purpose Input Output 39
EQEP1_INDEX 9, 14 I/O eQEP-1 Index
SYNCOUT 13 O External MCPWM Synchronization Pulse
GPIO40 0, 4, 8, 12 I/O General-Purpose Input Output 40
MCPWM1_2B 5 O MCPWM-1 Output 2B
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
GPIO41 0, 4, 8, 12 I/O General-Purpose Input Output 41
MCPWM3_1A 1 O MCPWM-3 Output 1A
SPIA_CLK 2 I/O SPI-A Clock
MCPWM1_2A 5 O MCPWM-1 Output 2A
SCIB_RX 9 I SCI-B Receive Data
EQEP1_B 10 I eQEP-1 Input B
GPIO43 0, 4, 8, 12 36 24 I/O General-Purpose Input Output 43
OUTPUTXBAR6 3 O Output X-BAR Output 6
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
UARTA_TX 7 O UART-A Transmit Data
EQEP1_INDEX 10 I/O eQEP-1 Index
GPIO45 0, 4, 8, 12 45 I/O General-Purpose Input Output 45
OUTPUTXBAR8 3 O Output X-BAR Output 8
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
GPIO46 0, 4, 8, 12 I/O General-Purpose Input Output 46
GPIO224 0, 4, 8, 12 6 4 4 I/O General-Purpose Input Output 224 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
MCPWM1_1A 9 O MCPWM-1 Output 1A
EQEP1_A 11 I eQEP-1 Input A
UARTA_TX 14 O UART-A Transmit Data
GPIO226 0, 4, 8, 12 4 2 2 I/O General-Purpose Input Output 226 This pin also has analog functions which are described in the ANALOG section of this table.
SPIA_CLK 6 I/O SPI-A Clock
MCPWM1_1B 9 O MCPWM-1 Output 1B
EQEP1_STROBE 11 I/O eQEP-1 Strobe
UARTA_RX 14 I UART-A Receive Data
GPIO227 0, 4, 8, 12 20 13 13 I/O General-Purpose Input Output 227 This pin also has analog functions which are described in the ANALOG section of this table.
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
MCPWM1_3A 3 O MCPWM-1 Output 3A
OUTPUTXBAR1 5 O Output X-BAR Output 1
MCPWM1_2B 6 O MCPWM-1 Output 2B
GPIO228 0, 4, 8, 12 4 2 2 I/O General-Purpose Input Output 228 This pin also has analog functions which are described in the ANALOG section of this table.
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
MCPWM1_2B 9 O MCPWM-1 Output 2B
EQEP1_B 11 I eQEP-1 Input B
GPIO230 0, 4, 8, 12 21 13 13 I/O General-Purpose Input Output 230 This pin also has analog functions which are described in the ANALOG section of this table.
I2CA_SDA 1, 7 I/OD I2C-A Open-Drain Bidirectional Data
MCPWM1_3B 3 O MCPWM-1 Output 3B
MCPWM1_2A 6 O MCPWM-1 Output 2A
GPIO242 0, 4, 8, 12 5 3 3 I/O General-Purpose Input Output 242 This pin also has analog functions which are described in the ANALOG section of this table.
MCPWM1_2A 3 O MCPWM-1 Output 2A
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIA_PTE 6 I/O SPI-A Peripheral Transmit Enable (PTE)
EQEP1_INDEX 11 I/O eQEP-1 Index
GPIO243 0, 4, 8, 12 I/O General-Purpose Input Output 243
XCLKOUT 1 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
TEST, JTAG, AND RESET
TCK 28 16 16 I JTAG test clock with internal pullup.
TMS 30 18 18 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
XRSn 3 1 1 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDDA 18 11 11 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. On the 32 QFN package, VREFHI is internally tied to VDDA. See the Power Management Module (PMM) section for usage details.
VDDIO 35, 46 23 23 3.3-V Digital I/O Power Pins. See the Power Management Module (PMM) section for usage details.
VSS 22, 37, 44 24, 29 PAD Digital Ground. For QFN packages, the ground pad on the bottom of the package must be soldered to the ground plane of the PCB.
VSSA 17 10 10 Analog Ground