SPRSPB9B July   2025  – October 2025 F28E120SB , F28E120SC

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and PWM X-BAR
      6. 5.4.6 GPIO and ADC Allocation
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - Internal Supply
      2. 6.4.2 Operating Mode Test Description
      3. 6.4.3 Current Consumption Graphs
      4. 6.4.4 Reducing Current Consumption
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PT Package
    7. 6.7  Thermal Resistance Characteristics for VFC Package
    8. 6.8  Thermal Resistance Characteristics for RHB Package
    9. 6.9  Thermal Design Considerations
    10. 6.10 System
      1. 6.10.1  Power Management Module (PMM)
        1. 6.10.1.1 Introduction
        2. 6.10.1.2 Overview
          1. 6.10.1.2.1 Power Rail Monitors
            1. 6.10.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.10.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
          2. 6.10.1.2.2 External Supervisor Usage
          3. 6.10.1.2.3 Delay Blocks
        3. 6.10.1.3 External Components
          1. 6.10.1.3.1 Decoupling Capacitors
            1. 6.10.1.3.1.1 VDDIO Decoupling
        4. 6.10.1.4 Power Sequencing
          1. 6.10.1.4.1 Supply Pins Ganging
          2. 6.10.1.4.2 Signal Pins Power Sequence
          3. 6.10.1.4.3 Supply Pins Power Sequence
            1. 6.10.1.4.3.1 Internal Power-Up Sequence
            2. 6.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.10.1.4.3.3 Supply Slew Rate
        5. 6.10.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.10.1.6 Power Management Module Electrical Data and Timing
          1. 6.10.1.6.1 Power Management Module Operating Conditions
          2. 6.10.1.6.2 Power Management Module Characteristics
      2. 6.10.2  Reset Timing
        1. 6.10.2.1 Reset Sources
        2. 6.10.2.2 Reset Electrical Data and Timing
          1. 6.10.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.10.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.10.2.2.3 Reset Timing Diagrams
      3. 6.10.3  Clock Specifications
        1. 6.10.3.1 Clock Sources
        2. 6.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.10.3.2.1.1 Input Clock Frequency
            2. 6.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.10.3.2.1.3 X1 Timing Requirements
            4. 6.10.3.2.1.4 PLL Characteristics
            5. 6.10.3.2.1.5 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            6. 6.10.3.2.1.6 Internal Clock Frequencies
        3. 6.10.3.3 Input Clocks and PLLs
        4. 6.10.3.4 XTAL Oscillator
          1. 6.10.3.4.1 Introduction
          2. 6.10.3.4.2 Overview
            1. 6.10.3.4.2.1 Electrical Oscillator
              1. 6.10.3.4.2.1.1 Modes of Operation
                1. 6.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.10.3.4.2.2 Quartz Crystal
          3. 6.10.3.4.3 Functional Operation
            1. 6.10.3.4.3.1 ESR – Effective Series Resistance
            2. 6.10.3.4.3.2 Rneg – Negative Resistance
            3. 6.10.3.4.3.3 Start-up Time
              1. 6.10.3.4.3.3.1 X1/X2 Precondition
            4. 6.10.3.4.3.4 DL – Drive Level
          4. 6.10.3.4.4 How to Choose a Crystal
          5. 6.10.3.4.5 Testing
          6. 6.10.3.4.6 Common Problems and Debug Tips
          7. 6.10.3.4.7 Crystal Oscillator Specifications
            1. 6.10.3.4.7.1 Crystal Oscillator Parameters
            2. 6.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.10.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.10.3.5 Internal Oscillators
          1. 6.10.3.5.1 System Oscillator SYSOSC
          2. 6.10.3.5.2 Wide Range Oscillator WROSC
      4. 6.10.4  Flash Parameters
        1. 6.10.4.1 Flash Parameters 
      5. 6.10.5  RAM Specifications
      6. 6.10.6  ROM Specifications
      7. 6.10.7  Emulation/JTAG
        1. 6.10.7.1 JTAG Electrical Data and Timing
          1. 6.10.7.1.1 JTAG Timing Requirements
          2. 6.10.7.1.2 JTAG Switching Characteristics
          3. 6.10.7.1.3 JTAG Timing Diagram
        2. 6.10.7.2 cJTAG Electrical Data and Timing
          1. 6.10.7.2.1 cJTAG Timing Requirements
          2. 6.10.7.2.2 cJTAG Switching Characteristics
          3. 6.10.7.2.3 cJTAG Timing Diagram
      8. 6.10.8  GPIO Electrical Data and Timing
        1. 6.10.8.1 GPIO – Output Timing
          1. 6.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.10.8.1.2 General-Purpose Output Timing Diagram
        2. 6.10.8.2 GPIO – Input Timing
          1. 6.10.8.2.1 General-Purpose Input Timing Requirements
          2. 6.10.8.2.2 Sampling Mode
        3. 6.10.8.3 Sampling Window Width for Input Signals
      9. 6.10.9  Interrupts
        1. 6.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.10.9.1.1 External Interrupt Timing Requirements
          2. 6.10.9.1.2 External Interrupt Switching Characteristics
          3. 6.10.9.1.3 External Interrupt Timing
      10. 6.10.10 Low-Power Modes
        1. 6.10.10.1 Clock-Gating Low-Power Modes
        2. 6.10.10.2 Low-Power Mode Wake-up Timing
          1. 6.10.10.2.1 IDLE Mode Timing Requirements
          2. 6.10.10.2.2 IDLE Mode Switching Characteristics
          3. 6.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.10.10.2.4 STANDBY Mode Timing Requirements
          5. 6.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.10.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.10.10.2.7 HALT Mode Timing Requirements
          8. 6.10.10.2.8 HALT Mode Switching Characteristics
          9. 6.10.10.2.9 HALT Entry and Exit Timing Diagram
    11. 6.11 Analog Peripherals
      1. 6.11.1 Analog Pins and Internal Connections
      2. 6.11.2 Analog-to-Digital Converter (ADC)
        1. 6.11.2.1 ADC Configurability
          1. 6.11.2.1.1 Signal Mode
        2. 6.11.2.2 ADC Electrical Data and Timing
          1. 6.11.2.2.1 ADC Operating Conditions
          2. 6.11.2.2.2 ADC Characteristics
          3. 6.11.2.2.3 ADC INL and DNL
          4. 6.11.2.2.4 ADC Performance Per Pin
          5. 6.11.2.2.5 ADC Input Model
          6. 6.11.2.2.6 ADC Timing Diagrams
      3. 6.11.3 Comparator Subsystem (CMPSS_LITE)
        1. 6.11.3.1 COMPDACOUT
        2. 6.11.3.2 CMPSS Connectivity Diagram
        3. 6.11.3.3 Block Diagram
        4. 6.11.3.4 CMPSS Electrical Data and Timing
          1. 6.11.3.4.1 CMPSS_LITE Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.11.3.4.2 CMPSS_LITE DAC Static Electrical Characteristics
          4. 6.11.3.4.3 CMPSS Illustrative Graphs
          5. 6.11.3.4.4 Buffered Output from CMPx_LITE_DACL Operating Conditions
          6. 6.11.3.4.5 Buffered Output from CMPx_LITE_DACL Electrical Characteristics
      4. 6.11.4 Programmable Gain Amplifier (PGA)
        1. 6.11.4.1 PGA Electrical Data and Timing
          1. 6.11.4.1.1 PGA Operating Conditions
          2. 6.11.4.1.2 PGA Characteristics
      5. 6.11.5 Temperature Sensor
        1. 6.11.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.11.5.1.1 Temperature Sensor Characteristics
    12. 6.12 Control Peripherals
      1. 6.12.1 Multichannel Pulse Width Modulator (MCPWM)
        1. 6.12.1.1 Control Peripherals Synchronization
        2. 6.12.1.2 MCPWM Electrical Data and Timing
          1. 6.12.1.2.1 MCPWM Timing Requirements
          2. 6.12.1.2.2 MCPWM Switching Characteristics
          3. 6.12.1.2.3 Trip-Zone Input Timing
            1. 6.12.1.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      2. 6.12.2 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.12.2.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.12.2.2 ADCSOCAO or ADCSOCBO Timing Diagram
      3. 6.12.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.12.3.1 eQEP Electrical Data and Timing
          1. 6.12.3.1.1 eQEP Timing Requirements
          2. 6.12.3.1.2 eQEP Switching Characteristics
      4. 6.12.4 Enhanced Capture (eCAP)
        1. 6.12.4.1 eCAP Block Diagram
        2. 6.12.4.2 eCAP Synchronization
        3. 6.12.4.3 eCAP Electrical Data and Timing
          1. 6.12.4.3.1 eCAP Switching Characteristics
    13. 6.13 Communications Peripherals
      1. 6.13.1 Inter-Integrated Circuit (I2C)
        1. 6.13.1.1 I2C Electrical Data and Timing
          1. 6.13.1.1.1 I2C Timing Requirements
          2. 6.13.1.1.2 I2C Switching Characteristics
          3. 6.13.1.1.3 I2C Timing Diagram
      2. 6.13.2 Universal Asynchronous Receiver-Transmitter (UART)
      3. 6.13.3 Serial Peripheral Interface (SPI)
        1. 6.13.3.1 SPI Controller Mode Timings
          1. 6.13.3.1.1 SPI Controller Mode Timing Requirements
          2. 6.13.3.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.13.3.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.13.3.1.4 SPI Controller Mode Timing Diagrams
        2. 6.13.3.2 SPI Peripheral Mode Timings
          1. 6.13.3.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.13.3.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.13.3.2.3 SPI Peripheral Mode Timing Diagrams
      4. 6.13.4 Serial Communications Interface (SCI)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Memory
      1. 7.2.1 C28x Memory Map
        1. 7.2.1.1 Dedicated RAM (Mx RAM)
      2. 7.2.2 Flash Memory Map
      3. 7.2.3 Peripheral Registers Memory Map
    3. 7.3  Identification
    4. 7.4  C28x Processor
      1. 7.4.1 Floating-Point Unit (FPU)
    5. 7.5  Direct Memory Access (DMA)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
  • PT|48
  • VFC|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.11.2.2.2 ADC Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
ADCCLK Conversion Cycles (5) 160-MHz SYSCLK 12 ADCCLKs
Power Up Time External Reference mode 500 µs
Internal Reference mode 5000 µs
Internal Reference mode, when switching between 2.5-V range and 3.3-V range. 5000 µs
VREFHI input current(1) 2.5 Reference 200 µA
1.65 Reference 130
Internal Reference Capacitor Value(2) 2.2 µF
External Reference Capacitor Value(2) 2.2 µF
DC Characteristics
Gain Error Internal reference -45 45 LSB
External reference -5 5
Offset Error -5 5 LSB
Channel-to-Channel Gain Error(4) 2 LSB
Channel-to-Channel Offset Error(4) 2 LSB
DNL Error >-1 1 LSB
INL Error -2 2 LSB
AC Characteristics
SNR(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 67.08 dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from SYSOSCDIV4 62.3
THD(3) VREFHI = 2.5 V, fin = 100 kHz –77 dB
SFDR(3) VREFHI = 2.5 V, fin = 100 kHz 82 dB
SINAD(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 66.8 dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from SYSOSCDIV4 62.14
ENOB(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, Single ADC 10.8 bits
PSRR VDDA = 3.3-V DC + 200 mV

DC up to Sine at 1 kHz		 60 dB
PSRR VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz		 57 dB
(1) Load current on VREFHI increases when ADC input is greater than VDDA.  This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.    
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk.
(4) Variation across all channels belonging to the same ADC module.
(5) Using SAMPCAPRESET feature; SAMPCAPRESETSEL = 1 and SAMPCAPRESETDISABLE = 0 inside the corresponding ADCSOCxCTL register.