SNVSCF0 October   2024 LM65680-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  EN Pin and Use as VIN UVLO
      3. 7.3.3  Device Configuration
      4. 7.3.4  Single-Output Dual-Phase Operation
      5. 7.3.5  Mode Selection
        1. 7.3.5.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.5.2 Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage (BST Pin)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Safety Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup
        4. 7.3.11.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Feed-forward Capacitor (CFF)
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Choosing the Switching Frequency
        6. 8.2.2.6 Setting the Output Voltage
        7. 8.2.2.7 Compensation Components
        8. 8.2.2.8 CBST
        9. 8.2.2.9 External UVLO
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, FSW = 2.2MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN PIN)
VINUVLO(R) VIN UVLO rising threshold VIN rising (Needed to start up) 3.3 3.4 3.45 V
VINUVLO(F) VIN UVLO falling threshold VIN falling (Once operating) 2.5 2.55 V
VINUVLO(H) VIN UVLO hysteresis 0.9 V
IVIN VIN pin input current, internal COMP, no switching  VBIAS = 3.3V + 2%, CONFIG short to VCC,  0.9 1.4 µA
IBIAS(FIX-3.3V) BIAS pin input current, fixed 3.3V output, internal COMP, no switching VBIAS = 3.3 V + 2%, CONFIG short to VCC, Auto Mode enabled  8.4 10 µA
IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, internal COMP, no switching VIN = 24V, VBIAS = 3.3V + 2%, CONFIG short to VCC, TJ = 25℃, auto mode enabled  2.1 2.7 µA
All temperatures 2.1 6.4 µA
IBIAS(ADJ-3.3V) BIAS pin input current, adjustable 3.3V output, internal COMP, no switching VFB = 0.8V + 2%, CONFIG short to VCC, auto mode enabled  6.8 8.1 µA
IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, internal COMP, no switching VIN = 24.0V, VFB = 0.8V + 2%, CONFIG short to VCC, auto mode enabled  1.9 2.5 µA
IBIAS(ADJ-3.3V-EXT) BIAS pin input current, adjustable 3.3V output, external COMP, no switching VFB = 0.8V + 2%, RCFG = 49.9kΩ, auto mode enabled  37 44 µA
IQ(ADJ-3.3V-EXT) Total VIN quiescent current, adjustable 3.3V output, external COMP, no  switching VIN = 24.0V, VFB=0.8V + 2%, RCFG = 49.9kΩ, auto mode enabled 6 7.4 µA
IQ-SD VIN Shutdown supply current VEN = 0V, TJ = 25℃ 1.3 1.6 µA
ENABLE (EN PIN)
VEN-TH(R) Enable voltage rising threshold VEN rising 1.15 1.25 1.35 V
VEN-TH(F) Enable input low threshold VEN falling 0.9 1 1.1 V
VEN-HYS Enable voltage hysteresis 250 mV
IEN-LKG Enable input leakage current VEN = VIN 0.22 3.45 µA
INTERNAL LDO (VCC PIN)
VVCC Internal LDO output voltage 3.4V ≤ VIN ≤ 65V, VBIAS = 0V 3.3 V
3.4V ≤ VBIAS ≤ 30V 3.2 V
VVCC-UVLO(R) VCC UVLO rising threshold VCC undervoltage rising threshold, IVCC = 0A  3.3 3.4 3.5 V
V VCC-UVLO(H) VCC UVLO hysteresis 0.9 V
VOLTAGE REFERENCE (FB PIN)
VFB1 Internal feedback reference voltage, internal compensation FPWM Mode, CONFIG shorted to VCC 0.792 0.8 0.808 V
VFB2 Internal feedback reference voltage, external compensation FPWM Mode, RCONFIG = 49.9kΩ 0.792 0.8 0.808 V
IFB-LKG Feedback pin input leakage current VFB = 0.8V, adjustable VOUT setting 0.025 90 nA
RFB-SEL-ADJ Adjustable output voltage setting resistance (thevenin equivalent) Resistor ladder between VOUT and GND, center tap connected to FB 4 100 kΩ
FIXED OUTPUT VOLTAGE (BIAS PIN)
VOUT1(3.3V) 3.3V fixed output voltage, internal COMP FB shorted to GND, CONFIG shorted to VCC 3.267 3.3 3.333 V
VOUT2(3.3V) 3.3V fixed output voltage, external COMP FB shorted to GND, RCONFIG = 49.9kΩ 3.267 3.3 3.333 V
VOUT1(5V) 5.0V fixed output voltage, internal COMP FB shorted to VCC, CONFIG shorted to VCC 4.95 5 5.05 V
VOUT2(5V) 5.0V fixed output voltage, external COMP FB shorted to VCC, RCONFIG = 49.9kΩ 4.95 5 5.05 V
STARTUP (SS PIN)
tEN_HIGH Enable HIGH to start of switching delay VFB = VRT = VMODE = GND,  VBIAS = VOUT 2.5 ms
tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% of set point 2.9 5.3 8.1 ms
ISS Soft-start charge current VSS = 0V 20 µA
RSS Soft-start discharge resistor EN = 0V 7 Ω
VSS(TH) Soft-start multiphase comparator threshold RCONFIG = 49.9kΩ 60 mV
ERROR AMPLIFIER (COMP PIN)
gm(EXTERNAL) EA transconductance – external COMP VCOMP = 0.8V, VFB = +5% & VFB = –5% 1 mS
VCOMP-EXT(h-clamp) External COMP-  high clamp voltage VFB = 0V, adjustable VOUT setting 1.056 V
CURRENT LIMITS AND HICCUP
IHS-LIM High-side peak current limit, 8A option Duty-cycle approaches 0%. 10.7 12.5 13.7 A
ILS-LIM Low-side valley current limit, 8A option 8.8 9.9 10.7 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty-cycle, 8A option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 2.4 3 3.7 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty-cycle, 8A option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 1.1 A
IHS-LIM High-side peak current limit, 6A option Duty-cycle approaches 0%. 8.2 9.5 10.6 A
ILS-LIM Low-side valley current limit, 6A option 6.6 7.4 8 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty-cycle, 6A option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 1.8 2.3 2.7 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty-cycle, 6A option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.95 A
IHS-LIM High-side peak current limit, 4A option Duty-cycle approaches 0%. 6.1 7 7.8 A
ILS-LIM Low-side valley current limit, 4A option 4.8 5.4 5.8 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty-cycle, 4A option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 1.3 1.8 2.1 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty-cycle, 4A option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.65 A
ILS-NEG-LIM Low-side negative current limit Sinking current limit, FPWM mode –9.6 –6.9 –4.9 A
IL-ZC-LIM Zero-cross current limit VVCC = 3.3V, auto mode 100 mA
VHIC Overcurrent hiccup threshold on FB pin Low-side FET ON-time > 165ns, after soft start 0.32 V
tHIC_DLY Hiccup mode activation delay 64 cycles
tHIC Hiccup mode duration time 40 ms
POWER GOOD MONITOR (PG PIN)
VPG-OVP(R) PG overvoltage rising threshold % of FB voltage (Adj) or BIAS voltage (Fixed) 103 105 107 %
VPG-OVP(F) PG overvoltage falling threshold % of FB voltage (Adj) or BIAS voltage (Fixed) 102 104 106 %
VPG-UVP(R) PG undervoltage rising threshold % of FB voltage (Adj) or BIAS voltage (Fixed) 94 96 98 %
VPG-UVP(F) PG undervoltage falling threshold % of FB voltage (Adj) or BIAS voltage (Fixed) 93 95 97 %
tPG-DEGLITCH(F) Deglitch filter delay on PG falling edge 55 114 175 µs
tPG-DEGLITCH(R) Deglitch filter delay on PG rising edge 1.2 2 3 ms
VIN(PG-VALID) Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU =  50kΩ, VPU = 5V 1.25 V
VOL(PG) Output low voltage IOL = 1mA, VIN = 1.25V 0.4 V
RON(PG) PG FET ON resistance IPG = 1mA 39 110 Ω
SWITCHING FREQUENCY (RT PIN)
fSW1(FPWM) Switching frequency, FPWM operation RRT = GND 1.98 2.2 2.42 MHz
fSW2(FPWM) Switching frequency, FPWM operation RRT = 15.8kΩ, 1% 900 1000 1100 kHz
fSW3(FPWM) Switching frequency, FPWM operation RRT = VCC 360 400 440 kHz
SYNCHRONIZATION (MODE/SYNC PIN)
VIH(SYNC) SYNC input high level threshold 1.3 V
VIL(SYNC) SYNC input low level threshold 0.45 V
VOH(CLKOUT) CLKOUT output high level threshold IOH = -2mA 2.4 V
VOL(CLKOUT) CLKOUT output low level threshold IOL = 2mA 0.4 V
fSYNC-RANGE(FPWM) Synchronization frequency range for set 2.2MHz fSW RRT = 6.81kΩ, 1% 1.76 2.64 MHz
fSYNC-RANGE(FPWM) Synchronization frequency range for set 300kHz fSW RRT = 54.2kΩ, 1% 240 360 kHz
tSYNC(TON-MIN) Minimum positive pulse width of external sync signal 80 ns
tSYNC(TOFF-MIN) Minimum negative pulse width of external sync signal 80 ns
tSYNC-SW-DLY SYNC to SW delay time –22 22 ns
DUAL RANDOM SPREAD SPECTRUM
ΔfSS-LF Low-frequency triangular spread spectrum modulation range DRSS pin floating 17 %
fm-LF Triangular modulation frequency DRSS pin floating 3.6 6 8.4 kHz
ΔfSS-HF High-frequency pseudo-random spread spectrum modulation range DRSS pin floating 2 %
POWER STAGE
RDS-ON-HS High-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.3V 42 mΩ
RDS-ON-LS Low-side FET ON resistance 23 mΩ
tON-MIN(FPWM) Minimum on-time(1) FPWM: IOUT = 0A, RRT = 6.81kΩ 36 48 ns
tON-MIN(AUTO)
Minimum on-time(1) 
 		 AUTO: IOUT = 2A, RRT = 6.81kΩ 36 48 ns
tOFF-MIN Minimum off-time VIN = 4V, Fsw = 2.2MHz, RRT = 6.81kΩ 80 111 ns
tON-MAX Maximum on-time Fsw = 300kHz, RRT= 54.2kΩ 13.3 µs
THERMAL SHUTDOWN
TSD Thermal Shutdown(1) Shutdown threshold 155 165 177 ºC
Recovery threshold 156 ºC
(1) Specified by design.