JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics Dynamic Performance

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, Sample rate = 80 MSPS, ADC is configured in internal reference mode (unless otherwise noted). MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, LVDD = 1.8 V.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SNR Signal-to-noise ratio fin = 10 MHz, 65 MSPS 75.6 dBFS
fin = 5 MHz, TA = 25°C 72.8 75.5 dBFS
fin = 5 MHz, Across temperatures 71.8 dBFS
fin = 5 MHz, -60 dBFS Input signal amplitude 77.3 dBFS
fin = 5 MHz, Decimation by two enabled 78.2 dBFS
fin = 30 MHz 74.2 dBFS
fin = 65 MHz 71.7 dBFS
SINAD Signal-to-noise and distortion ratio fin = 5 MHz 74.8 dBFS
fin = 30 MHz 73.4 dBFS
fin = 65 MHz 70 dBFS
ENOB Effective number of bits fin = 5 MHz 12.2 Bits
DNL Differential nonlinearity fin = 5 MHz –0.96 ±0.5 1.7 LSB
INL Integral nonlinearity fin = 5 MHz 2.2 5.5 LSB
SFDR Spurious-free dynamic range fin = 5 MHz 72 84 dBc
fin = 30 MHz 81 dBc
fin = 65 MHz 74 dBc
THD Total harmonic distortion fin = 5 MHz 70.5 82 dBc
fin = 30 MHz 80 dBc
fin = 65 MHz 73.5 dBc
HD2 Second-harmonic distortion fin = 5 MHz 73 93 dBc
fin = 30 MHz 88 dBc
fin = 65 MHz 85 dBc
HD3 Third-harmonic distortion fin = 5 MHz 72 84 dBc
fin = 30 MHz 81 dBc
fin = 65 MHz 74 dBc
Worse spur excluding HD2, HD3 fin = 5 MHz 91 dBc
fin = 30 MHz 83 dBc
fin = 65 MHz 76 dBc
IMD3 Intermodualtion distortion fin = 8 MHz at –7 dBFS, f2 = 10 MHz at –7 dBFS 84.5 dBc
Overload recovery Recovery to within 1% of full-scale for 6-dB overload with sine wave input 1 Clock Cycle
XTALK Cross-talk fin = 10 MHz, –1-dBFS signal applied on aggressor channel no signal applied on victim channel far channel 90 dBc
near channel 85 dBc
Phase noise 5 MHz, 1-kHz off carrier –138 dBc/Hz
ANALOG INPUT / OUTPUT
Differential input voltage range
(0-dB gain)		 2 VPP
RIN Differential Input Resistance At DC 2 kΩ
CIN Differential Input Capacitance At DC 3.2 pF
Analog input bandwidth With a 50-Ω source impedance 550 MHz
Analog input common-mode current
(per input pin)		 1.6 µA/MSPS
VCM common-mode output voltage 0.95 V
VCM output current capability 5 mA
DC ACCURACY
Offset error Across devices and across channels within a device –15 15 mV
Temperature coefficient of offset error < 0.01 mV/ °C
E(GREF) Gain error due to internal reference inaccuracy alone Across devices –2 2 %FS
E(GCHAN) Gain error of channel alone 0.5 %FS
Temperature coefficient of E(GCHAN) < 0.01 %FS/ °C
POWER SUPPLY
Power consumption 80 MSPS, 14 Bit, 2-wire LVDS 77 mW/CH
50 MSPS, 1 wire LVDS 58 mW/CH
40 MSPS, 14 Bit, 1-wire LVDS 52 mW/CH
10 MSPS, 14 Bit, 1-wire LVDS 33 mW/CH
fin = 10 MHz, 80 MSPS, 14 Bit,
Decimation filter = 2, 1-wire LVDS		 100 mW/CH
AVDD 14 Bit, 80 MSPS 230 265 mA
14 Bit, 65 MSPS 200 mA
14 Bit, 40 MSPS 155 mA
LVDD 80 MSPS, 14 Bit, 2-wire LVDS(1) 111 122 mA
50 MSPS, 14 Bit, 1-wire LVDS 80 mA
40 MSPS, 14 Bit, 1-wire LVDS 73 mA
80 MSPS, 1 Bit, Decimation filter = 2,
1-wire LVDS		 210 mA
Power-down power consumption Partial Power Down (80 MSPS, 2-wire) 175 mW
Complete Power Down 60 mW
Power supply modulation ratio Carrier = 5 MHz, f(PSRR) = 10 kHz, 50 mVpp on AVDD 35 dB
Power supply rejection ratio AC power supply rejection ratio f = 10 kHz 55 dB
(1) The maximum limit used for the LVDD current at –40°C is 132 mA.