JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.1.16 Programmable Mapping Between Input Channels and Output Pins

Table 14. Mapping Between Input Channels and Output Pins

ADDR. (HEX) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME
50 1 X X X X MAP_CH1234_TO_OUT1A
1 X X X X MAP_CH1234_TO_OUT1B
1 X X X X MAP_CH1234_TO_OUT2A
51 1 X X X X MAP_CH1234_TO_OUT2B
1 X X X X MAP_CH1234_TO_OUT3A
1 X X X X MAP_CH1234_TO_OUT3B
52 1 X X X X MAP_CH1234_TO_OUT4A
1 X X X X MAP_CH1234_TO_OUT4B
53 1 X X X X MAP_CH5678_TO_OUT5B
1 X X X X MAP_CH5678_TO_OUT5A
1 X X X X MAP_CH5678_TO_OUT6B
54 1 X X X X MAP_CH5678_TO_OUT6A
1 X X X X MAP_CH5678_TO_OUT7B
1 X X X X MAP_CH5678_TO_OUT7A
55 1 X X X X MAP_CH5678_TO_OUT8B
1 X X X X MAP_CH5678_TO_OUT8A

The ADS5294 has 16 pairs of LVDS channel outputs. The mapping of ADC channels to LVDS output channels is programmable to allow for flexibility in board layout. The 16 LVDS channel outputs are split into two groups of eight LVDS pairs. Within each group four ADC input channels are multiplexed into the eight LVDS pairs depending on the modes of operation whether it is in 1-wire mode or 2-wire mode.

Input channels 1 to 4 map to any of the LVDS outputs OUT1A or OUT1B to OUT4A or OUT4B (using the MAP_CH1234_TO_OUTnA or OUTnB). Similarly, input channels 5 to 8 can be mapped to any of the LVDS outputs OUT5A or OUT5B to OUT8A or OUT8B (using the MAP_CH5678_TO_OUTnA or OUTnB). The block diagram of the mapping is listed in Figure 61.

ADS5294 channel_map_las776.gifFigure 61. Input and Output Channel Mapping

Registers 0x50 to 0x55 control the multiplexing options as shown in Table 12 and Table 13.

Table 12. Multiplexing Options

MAP_CH1234_to_OUTn<3:0> MAPPING USED IN 1-WIRE MODE? USED IN 2-WIRE MODE?
0000 ADC input channel IN1 to OUTn Y Y, for LSB byte
0001 ADC input channel IN1 to OUTn (2-wire only) N Y, for MSB byte
0010 ADC input channel IN2 to OUTn Y Y, for LSB byte
0011 ADC input channel IN2 to OUTn (2-wire only) N Y, for MSB byte
0100 ADC input channel IN3 to OUTn Y Y, for LSB byte
0101 ADC input channel IN3 to OUTn (2-wire only) N Y, for MSB byte
0110 ADC input channel IN4 to OUTn Y Y, for LSB byte
0111 ADC input channel IN4 to OUTn (2-wire only) N Y, for MSB byte
1xxx LVDS output buffer OUTn is powered down

Table 13. Multiplexing Options

MAP_CH5678_to_OUTn<3:0> MAPPING USED IN 1-WIRE MODE? USED IN 2-WIRE MODE?
0000 ADC input channel IN8 to OUTn Y Y, for LSB byte
0001 ADC input channel IN8 to OUTn (2-wire only) N Y, for MSB byte
0010 ADC input channel IN7 to OUTn Y Y, for LSB byte
0011 ADC input channel IN7 to OUTn (2-wire only) N Y, for MSB byte
0100 ADC input channel IN6 to OUTn Y Y, for LSB byte
0101 ADC input channel IN6 to OUTn (2-wire only) N Y, for MSB byte
0110 ADC input channel IN5 to OUTn Y Y, for LSB byte
0111 ADC input channel IN5 to OUTn (2-wire only) N Y, for MSB byte
1xxx LVDS output buffer OUTn is powered down

The default mapping for 1-wire and 2-wire modes is shown in Table 14 and Table 15.

Table 14. Mapping for 1-Wire Mode(1)

ANALOG INPUT CHANNEL LVDS OUTPUT
Channel IN1 OUT1A
Channel IN2 OUT2A
Channel IN3 OUT3A
Channel IN4 OUT4A
Channel IN5 OUT5A
Channel IN6 OUT6A
Channel IN7 OUT7A
Channel IN8 OUT8A
(1) 3In the single wire mode with default register settings, ADC data is available only on OUTnA.

Table 15. Mapping for 2-Wire Mode(1)

ANALOG INPUT CHANNEL LVDS OUTPUT
Channel IN1 OUT1A, OUT1B
Channel IN2 OUT2A, OUT2B
Channel IN3 OUT3A, OUT3B
Channel IN4 OUT4A, OUT4B
Channel IN5 OUT5A, OUT5B
Channel IN6 OUT6A, OUT6B
Channel IN7 OUT7A, OUT7B
Channel IN8 OUT8A, OUT8B
(1) In the 2-wire mode, the ADC data is available on both OUTnA and OUTnB.