JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

PFP Package
80-PIN TQFP With Thermal Pad
Top View
ADS5294 PINOUT.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AVDD 9, 52, 66, 71, 74 Analog power supply, 1.8 V
AGND 3, 6, 55, 58, 61, 80 Analog ground
VCM 68 Common-mode output pin, 0.95-V output. This pin can be configured as the external reference voltage (1.5 V) input pin as well. See Reg 0x42 and External Reference Mode of Operation.
CLKN 73 Negative differential clock –Tie CLKN to GND for single-ended clock
CLKP 72 Positive differential clock
IN1P, IN1N 78, 79 Differential input signal, Channel 1
IN2P, IN2N 1, 2 Differential input signal, Channel 2
IN3P, IN3N 4, 5 Differential input signal, Channel 3
IN4P, IN4N 7, 8 Differential input signal, Channel 4
IN5P, IN5N 53, 54 Differential input signal, Channel 5
IN6P, IN6N 56, 57 Differential input signal, Channel 6
IN7P, IN7N 59, 60 Differential input signal, Channel 7
IN8P, IN8N 62, 63 Differential input signal, Channel 8
LCLKP, LCLKN 31, 32 Differential LVDS bit clock (7X)
ACLKP, ACLKN 29, 30 Differential LVDS frame clock (1X)
OUT1A_P, OUT1A_N 13, 14 Differential LVDS data output, wire 1, channel 1
OUT1B_P, OUT1B_N 15, 16 Differential LVDS data output, wire 2, channel 1
OUT2A_P, OUT2A_N 17, 18 Differential LVDS data output, wire 1, channel 2
OUT2B_P, OUT2B_N 19, 20 Differential LVDS data output, wire 2, channel 2
OUT3A_P, OUT3A_N 21, 22 Differential LVDS data output, wire 1, channel 3
OUT3B_P, OUT3B_N 23, 24 Differential LVDS data output, wire 2, channel 3
OUT4A_P, OUT4A_N 25, 26 Differential LVDS data output, wire 1, channel 4
OUT4B_P, OUT4B_N 27, 28 Differential LVDS data output, wire 2, channel 4
OUT5A_P, OUT5A_N 35, 36 Differential LVDS data output, wire 1, channel 5
OUT5B_P, OUT5B_N 33, 34 Differential LVDS data output, wire 2, channel 5
OUT6A_P, OUT6A_N 39, 40 Differential LVDS data output, wire 1, channel 6
OUT6B_P, OUT6B_N 37, 38 Differential LVDS data output, wire 2, channel 6
OUT7A_P, OUT7A_N 43, 44 Differential LVDS data output, wire 1, channel 7
OUT7B_P, OUT7B_N 41, 42 Differential LVDS data output, wire 2, channel 7
OUT8A_P, OUT8A_N 47, 48 Differential LVDS data output, wire 1, channel 8
OUT8B_P, OUT8B_N 45, 46 Differential LVDS data output, wire 2, channel 8
PD 10 Power-down control input. Active High. The pin has an internal 220-kΩ pulldown resistor.
REFB 69 Negative reference input and output. Internal reference mode: Reference bottom voltage (0.45 V) is output on this pin. A decoupling capacitor is not required on this pin. External reference mode: Reference bottom voltage (0.45 V) must be externally applied to this pin. Please see External Reference Mode of Operation.
REFT 70 Positive reference input and output. Internal reference mode: Reference top voltage (1.45 V) is output on this pin. A decoupling capacitor is not required on this pin. External reference mode: Reference top voltage (1.45 V) must be externally applied to this pin. Please see External Reference Mode of Operation.
RESET 51 Active HIGH RESET input. The pin has an internal 220-kΩ pulldown resistor.
SCLK 77 Serial clock input. The pin has an internal 220-kΩ pulldown resistor.
SDATA 76 Serial data input. The pin has an internal 220-kΩ pulldown resistor.
SDOUT 64 Serial data readout. This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the SDOUT pin becomes active. SDOUT is a CMOS digital output running from the AVDD supply.
CSZ 75 Serial enable chip select – active-low digital input
SYNC 65 Input signal to synchronize channels and chips when used with reduced output data rates. If it is not used, add a ≤ 10-KΩ pulldown resistor.
LVDD 11, 49 Digital and I/O power supply, 1.8 V
LGND 12, 50 Digital ground
NC 67 No Connection. Must leave floated