JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.1.4 LVDS Test Patterns

Table 4. LVDS Test Patterns

ADDR. (HEX) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME
23 X X X X X X X X X X X X X X X X PRBS_SEED<15:0>
24 X X X X X X X PRBS_SEED<22:16>
25 X 0 0 EN_RAMP
0 X 0 DUALCUSTOM_PAT
0 0 X SINGLE_CUSTOM_PAT
X X BITS_CUSTOM1<13:12>
X X BITS_CUSTOM2<13:12>
X TP_SOFT_SYNC
X PRBS_TP_EN
X PRBS_MODE_2
X PRBS_SEED_FROM_REG
X TP_HARD_SYNC
26 X X X X X X X X X X X X BITS_CUSTOM1<11:0>
27 X X X X X X X X X X X X BITS_CUSTOM2<11:0>
45 0 X PAT_DESKEW
X 0 PAT_SYNC

The ADS5294 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. All these patterns can be synchronized across devices by the sync function either through the hardware SYNC pin or the software sync bit TP_SOFT_SYNC bit in register 0x25. When set, the TP_HARD_SYNC bit enables the test patterns to be synchronized by the hardware SYNC Pin. When the software sync bit TP_SOFT_SYNC is set, special timing is needed.

  • Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the full-scale code, it returns back to zero code and ramps again.
  • The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and programming the desired code in BITS_CUSTOM1<13:0>. In this mode, BITS_CUSTOM1<13:0> take the place of the 14-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes the same way as normal ADC data are controlled.
  • The device can also toggle between two consecutive codes, by programming DUAL_CUSTOM_PAT to '1'. The two codes are represented by the contents of BITS_CUSTOM1<13:0> and BITS_CUSTOM2<13:0>.
  • In addition to custom patterns, the device may also be made to output two preset patterns:
    • Deskew patten – Set using PAT_DESKEW, this mode replaces the 14-bit ADC output D<13:0> with the 0101010101010101 word.
    • Sync pattern – Set using PAT_SYNC, the normal ADC word is replaced by a fixed 11111110000000 word.
    • PRBS patterns – The device can give 9-bit or 23-bit LFSR Pseudo random pattern on the channel outputs that are controlled by the register 0x25. To enable the PRBS pattern PRBS_TP_EN bit in the register 0x25 needs to be set. The default is the 23-bit LFSR. To select the 9-bit LFSR, set the PRBS_MODE_2 bit. The seed value for the PRBS patterns can be chosen by enabling the PRBS_SEED_FROM_REG bit to 1 and the value written to the PRBS_SEED registers in 0x24 and 0x23.

NOTE

Only one of these patterns should be active at any given instant.