JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6 Register Maps

Table 6. Summary of Functions Supported by Serial Interface (1)(2)(3)(4)

ADDR. (HEX) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION
00 X RST 1: Self-clearing software RESET; . After reset, this bit is set to 0
0: Normal operation.
01 X EN_READOUT 1: READOUT of registers mode;0: Normal operation
X EN_HIGH_ADDRS 0 – Disable access to register at address 0xF0
1 – Enable access to register at address 0xF0
02 X EN_SYNC 1:Enable SYNC feature to synchronize the test patterns;
0: Normal operation, SYNC feature is disabled for the test patterns.
Note: this bit needs to be set as 1 when software or hardware SYNC feature is used. see Reg.0x25[8] and 0x25[15]
0A X X X X X X X X X X X X X X X X RAMP_PAT_RESET_VAL Ramp pattern reset value
0F X X X X X X X X PDN_CH<8:1> 1:Channel-specific ADC power-down mode;
0: Normal operation
X PDN_PARTIAL 1:Partial power-down mode - fast recovery from power-down;
0: Normal operation
X PDN_COMPLETE 1:Register mode for complete power-down - slower recovery;
0: Normal operation
X PDN_PIN_CFG 1:Configures PD pin for partial power-down mode;
0:Configures PD pin for complete power-down mode
14 X X X X X X X X LFNS_CH<8:1> 1: Channel-specific low-frequency noise suppression mode enable;
0: LFNS disabled
1C X EN_FRAME_PAT 1: Enables output frame clock to be programmed through a pattern; 0: Normal operation on frame clock
X X X X X X X X X X X X X X ADCLKOUT<13:0> 14-bit pattern for frame clock on ADCLKP and ADCLKN pins
23 X X X X X X X X X X X X X X X X PRBS_SEED<15:0> PRBS pattern starting seed value lower 16 bits
24 X X X X X X X X INVERT_CH<8:1> 1: Swaps the polarity of the analog input pins electrically;
0: Normal configuration
X X X X X X X PRBS_SEED<22:16> PRBS seed starting value upper 7 bits
25 X 0 0 EN_RAMP 1: Enables a repeating full-scale ramp pattern on the outputs;
0: Normal operation
0 X 0 DUALCUSTOM_PAT 1:Enables mode wherein output toggles between two defined codes;
0: Normal operation
0 0 X SINGLE_CUSTOM_PAT 1: Enables mode wherein output is a constant specified code;
0: Normal operation
X X BITS_CUSTOM1<13:12> 2 MSBs for single custom pattern (and for the first code of the dual custom patterns)
X X BITS_CUSTOM2<13:12> 2 MSBs for second code of the dual custom patterns
X TP_SOFT_SYNC 1: Software sync bit for test patterns on all 8 CHs;
0: No sync. Note: in order to synchronize the digital filters using the SYNC pin, this bit must be set as 0.
X PRBS_TP_EN 1: PRBS test pattern enable bit;
0: PRBS test pattern disabled
X PRBS_MODE_2 PRBS 9 bit LFSR (23bit LFSR is default)
X PRBS_SEED_FROM_REG 1: Enable PRBS seed to be chosen from register 0x23 and 0x24;
0: Disabled
X TP_HARD_SYNC 1: Enable the external SYNC feature for syncing test patterns.
0: Inactive. Note: in order to synchronize the digital filters using the SYNC pin, this bit must be set as 0.
26 X X X X X X X X X X X X BITS_CUSTOM1<11:0> 12 lower bits for single custom pattern (and for the first code of the dual custom pattern).
27 X X X X X X X X X X X X BITS_CUSTOM2<11:0> 12 lower bits for second code of the dual custom pattern
28 X EN_BITORDER Enables the bit order output.
0 = byte-wise, 1 = word-wise or bit-wise
X X BIT_WISE Selects between byte-wise and bit-wise
1: bit-wise, odd bits come out on one wire and even bits come out on other wire. D15 must be set to '1' for the bit-wise mode.
0: byte-wise, upper bits on one wire and lower bits on other wire
D15 must be set to '0' for the byte-wise mode.
1 X X X X X X X X EN_WORDWISE__BY_CH<7:0> 1: Output format is one sample on one LVDS wire and next sample on other LVDS wire.
0: Data comes out in 2-wire mode with upper set of bits on one channel and lower set of bits on the other.
Note: D15 must set to '1' for the word-wise mode.
29 X GLOBAL_EN_FILTER 1: Enables filter blocks - global control;
0: Inactive
X EN_CHANNEL_AVG 1: Enables channel averaging mode;
0: Inactive
2A X X X X GAIN_CH1<3:0> Programmable gain - Channel 1
X X X X GAIN_CH2<3:0> Programmable gain - Channel 2
X X X X GAIN_CH3<3:0> Programmable gain - Channel 3
X X X X GAIN_CH4<3:0> Programmable gain - Channel 4
2B X X X X GAIN_CH5<3:0> Programmable gain - Channel 5
X X X X GAIN_CH6<3:0> Programmable gain - Channel 6
X X X X GAIN_CH7<3:0> Programmable gain - Channel 7
X X X X GAIN_CH8<3:0> Programmable gain - Channel 8
2C X X AVG_CTRL4<1:0> Averaging control for what comes out on LVDS output OUT4
X X AVG_CTRL3<1:0> Averaging control for what comes out on LVDS output OUT3
X X AVG_CTRL2<1:0> Averaging control for what comes out on LVDS output OUT2
X X AVG_CTRL1<1:0> Averaging control for what comes out on LVDS output OUT1
2D X X AVG_CTRL8<1:0> Averaging control for what comes out on LVDS output OUT8
X X AVG_CTRL7<1:0> Averaging control for what comes out on LVDS output OUT7
X X AVG_CTRL6<1:0> Averaging control for what comes out on LVDS output OUT6
X X AVG_CTRL5<1:0> Averaging control for what comes out on LVDS output OUT5
2E X X X FILTER1_COEFF_SET<2:0> Select stored coefficient set for filter 1
X X X FILTER1_RATE<2:0> Set decimation factor for filter 1
X ODD_TAP1 Use odd tap filter 1
X USE_FILTER1 1: Enables filter for channel 1;
0: Disables
X X X X HPF_CORNER _CH1 HPF corner in values k from 2 to 10
X HPF_EN_CH1 1: HPF filter enable for the channel;
0: Disables
2F X X X FILTER2_COEFF_SET<2:0> Select stored coefficient set for filter 2
X X X FILTER2_RATE<2:0> Set decimation factor for filter 2
X ODD_TAP2 Use odd tap filter 2
X USE_FILTER2 1: Enables filter for channel 2;
0: Disables
X X X X HPF_CORNER _CH2 HPF corner in values k from 2 to 10
X HPF_EN_CH2 1: HPF filter enabled for the channel;
0: Disabled
30 X X X FILTER3_COEFF_SET<2:0> Select stored coefficient set for filter 3
X X X FILTER3_RATE<2:0> Set decimation factor for filter 3
X ODD_TAP3 Use odd tap filter 3
X USE_FILTER3 1: Enables filter for channel 3;
0: Disables
X X X X HPF_CORNER _CH3 HPF corner in values k from 2 to 10
X HPF_EN_CH3 1: HPF filter enabled for the channel;
0: Disabled
31 X X X FILTER4_COEFF_SET<2:0> Select stored coefficient set for filter 4
X X X FILTER4_RATE<2:0> Set decimation factor for filter 4
X ODD_TAP4 Use odd tap filter 4
X USE_FILTER4 1: Enables filter for channel 4;
0: Disables
X X X X HPF_CORNER _CH4 HPF corner in values k from 2 to 10
X HPF_EN_CH4 1: HPF filter enabled for the channel;
0: Disabled
32 X X X FILTER5_COEFF_SET<2:0> Select stored coefficient set for filter 5
X X X FILTER5_RATE<2:0> Set decimation factor for filter 5
X ODD_TAP5 Use odd tap filter 5
X USE_FILTER5 1: Enables filter for channel 5;
0: Disables
X X X X HPF_CORNER _CH5 HPF corner in values k from 2 to 10
X HPF_EN_CH5 1: HPF filter enabled for the channel;
0: Disabled
33 X X X FILTER_TYPE6<2:0> Select stored coefficient set for filter 6
X DECBY8_6 Enables decimate by 8 filter 6
X X FILTER_MODE6<1:0> Set decimation factor for filter 6
X ODD_TAP6 Use odd tap filter 6
X USE_FILTER6 Enables filter for channel 6
X X X X HPF_CORNER _CH6 HPF corner in values k from 2 to 10
X HPF_EN_CH6 HPF filter enable for the channel
34 X X X FILTER_TYPE7<2:0> Select stored coefficient set for filter 7
X DECBY8_7 Enables decimate by 8 filter 7
X X FILTER_MODE7<1:0> Set decimation factor for filter 7
X ODD_TAP7 Use odd tap filter 7
X USE_FILTER7 Enables filter for channel 7
X X X X HPF_CORNER _CH7 HPF corner in values k from 2 to 10
X HPF_EN_CH7 HPF filter enable for the channel
35 X X X FILTER_TYPE8<2:0> Select stored coefficient set for filter 8
X DECBY8_8 Enables decimate by 8 filter 8
X X FILTER_MODE8<1:0> Set decimation factor for filter 8
X ODD_TAP8 Use odd tap filter 8
X USE_FILTER8 1: Enables filter for channel 8;
0: Disables
X X X X HPF_CORNER_CH8 HPF corner in values k from 2 to 10
X HPF_EN_CH8 1: HPF filter enable for the channel;
0: Disables
38 X X DATA_RATE<1:0> Select output frame clock rate. Please see Output Data Rate Control.
42 X X EXT_REF_VCM Drive external reference mode through:
D15 = D3 = 1: the VCM pin;
D15 = D3 = 0: REFT and REFB pins.
Note: 0xF0[15] should be set as '1' to enable the external reference mode.
X X PHASE_DDR<1:0> Controls phase of LCLK output relative to data
45 0 X PAT_DESKEW 1: Enable deskew pattern mode;
0: Inactive
X 0 PAT_SYNC 1: Enable sync pattern mode;
0: Inactive
46 1 X EN_2WIRE 1: 2-wire LVDS output;
0: 1-wire LVDS output.
Note: ~250us PLL settling time is required after programming the EN_2WIRE bit from Default States After Reset.
1 X BTC_MODE 1: 2s complement; (ADC data output format)
0: Binary Offset (ADC data output format)
1 X MSB_FIRST 1: MSB First;
0: LSB First
1 X EN_SDR 1:SDR Bit Clock;
0: DDR Bit Clock
1 X X X X EN_BIT_SER Output serialization mode.
0001: 10 bit (EN_10BIT)
0010: 12 bit (EN_12BIT)
0100: 14 bit (EN_14BIT)
1000: 16 bit (EN_16BIT)
1 X FALL_SDR 1: Controls LCLK rising or falling edge comes in the middle of data window when operating in SDR output mode; 0: At the edge of data window.
50 1 X X X X MAP_Ch1234_to_OUT1A OUT1A Pin pair to channel data mapping selection
1 X X X X MAP_Ch1234_to_OUT1B OUT1B Pin pair to channel data mapping selection
1 X X X X MAP_Ch1234_to_OUT2A OUT2A Pin pair to channel data mapping selection
51 1 X X X X MAP_Ch1234_to_OUT2B OUT2B Pin pair to channel data mapping selection
1 X X X X MAP_Ch1234_to_OUT3A OUT3A Pin pair to channel data mapping selection
1 X X X X MAP_Ch1234_to_OUT3B OUT3B Pin pair to channel data mapping selection
52 1 X X X X MAP_Ch1234_to_OUT4A OUT4A Pin pair to channel data mapping selection
1 X X X X MAP_Ch1234_to_OUT4B OUT4B Pin pair to channel data mapping selection
53 1 X X X X MAP_Ch5678_to_OUT5B OUT5B Pin pair to channel data mapping selection
1 X X X X MAP_Ch5678_to_OUT5A OUT5A Pin pair to channel data mapping selection
1 X X X X MAP_Ch5678_to_OUT6B OUT6B Pin pair to channel data mapping selection
54 1 X X X X MAP_Ch5678_to_OUT6A OUT6A Pin pair to channel data mapping selection
1 X X X X MAP_Ch5678_to_OUT7B OUT7B Pin pair to channel data mapping selection
1 X X X X MAP_Ch5678_to_OUT7A OUT7A Pin pair to channel data mapping selection
55 1 X X X X MAP_Ch5678_to_OUT8B OUT8B Pin pair to channel data mapping selection
1 X X X X MAP_Ch5678_to_OUT8A OUT8A Pin pair to channel data mapping selection
F0 X EN_EXT_REF 1: Enable external reference mode. the voltage reference can be applied on either REFP and REFB pins or VCM pin.
0: Default: internal reference mode.
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2) X = Register bit referenced by the corresponding name and description
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4) Multiple functions in a register can be programmed in a single write operation.