JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.9 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled

See (1)
ADC CLK Frequency (MSPS) Set-up Time (tsu), ns Hold Time (tH), ns tPROG = (5 / 7) × T + tdelay, ns(2)
Fs = 1 / T Data Valid to Zero-Crossing of LCLKP
(both edges)		 Zero-Crossing of LCLKP to Data Becoming Invalid
(both edges)		 tPROG = delay from Input clock zero-cross rising edge to frame clock zero cross (rising edge)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
50 0.28 0.48 0.28 0.6 7.5 9 10.5
40 0.5 0.68 0.54 0.8 7.5 9 10.5
30 0.62 0.8 1 1.25 7.5 9 10.5
20 1.2 1.4 1.6 1.9 7.5 9 10.5
10 3.1 3.3 3.3 3.5 7.5 9 10.5
(1) Bit clock and Frame clock jitter has been included in the Set-up and hold timing.
(2) Values below correspond to tdelay, NOT tPROG

NOTE

The LVDS timing specification is only valid when digital decimation filters are disabled. When digital filters are enabled, the set-up time decreases as the corresponding hold time increases as shown in LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled to LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled. The change on LVDS timing also depends on the internal PLL setting of the ADS5294. See PLL Operation Versus LVDS Timing for more information.

At the highest sampling frequency, 80-MSPS, and decimation of 2 ( for example: effective data rate = 560 Mbps in 1-wire mode), the set-up time is reduced by 70 ps, (for example: set-up time, min = 0.43 ns; hold time, min = 0.54 ns). scenario assumes that the recommended PLL settings are configured as shown in PLL Operation Versus LVDS Timing

ADS5294 reset_tim_las776.gif
1. A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. Tie RESET permanently HIGH for parallel interface operation.
2. SEN refers to the CSZ pin.
Figure 1. Reset Timing Diagram
ADS5294 LVDS_vo_lev_las776.gifFigure 2. LVDS Output Voltage Levels
ADS5294 LVDS_tim1_las776.gifFigure 3. 14-Bit 1-Wire LVDS Timing Diagram
ADS5294 LVDS_tim2_las776.gifFigure 4. Enlarged 1-Wire LVDS Timing Diagram (14 bit)
ADS5294 LVDS_tim3_las776.gifFigure 5. 14-Bit 2-Wire LVDS Timing Diagram
ADS5294 LVDS_tim4_las776.gifFigure 6. Enlarged 2-Wire LVDS Timing Diagram (14 bit)
ADS5294 LVDS_tim5_las776.gifFigure 7. Definition of Setup and Hold Times tSU = min(tSU1, tSU2); tH = min(tH1, tH2)