JAJSFA9E November 2011 – April 2018 ADS5294
PRODUCTION DATA.
The ADS5294 uses a PLL that automatically changes configuration to one of four states depending on the sampling clock frequency. The clock frequency detection is automatic and each time the sampling frequency crosses a threshold, the PLL changes configuration to a new state. The PLL remains in the new state for a range of clock frequencies. To prevent unwanted toggling of PLL state around a threshold, the circuit has an built-in hysteresis. The ADS5294 has three thresholds over the sampling clock frequency range from 10 MHz to 80 MHz and can be in one of four states as shown by Figure 50.
Each threshold shifts by a small amount across temperature. On power up, depending on the clock frequency, the PLL settles in one of four states. Later, as the system warms up, the PLL changes state once due to the shift in the threshold across temperature.