4 改訂履歴
Changes from D Revision (September 2015) to E Revision
- Added The maximum limit used for the LVDD current at –40°C is 132 mA table noteGo
- Added bypass decimation values to the DATA_RATE, FILTERn_RATE, and FILTERn_COEFF_SET columnsGo
- Changed D15 value of ADDR. (HEX) 28 to XGo
- Changed this to the byte-wise for clarificationGo
- Changed this to the word-wise for clarificationGo
- Changed D15 value to 1 in Bit-Byte-Word Wise Output tableGo
- Added DATA_RATE>, FILTERn_RATE, and FILTERn_COEFF_SET values to the bypass decimation row in the Digital Filters tableGo
Changes from C Revision (September 2013) to D Revision
- 「ピン構成および機能」セクション、「ESD定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加Go
- 「アプリケーション」に「ソナー・イメージング」を追加Go
- Updated Pinout.Go
- Added text note 2 to Figure 1Go
- Added a text note to Figure 44. Go
- Corrected typo in Table 1Go
- Added note to EN_2WIRE bit.Go
- Corrected typo in Table 9Go
Changes from B Revision (July 2012) to C Revision
- Added cross-reference link for VCM pin.Go
- Added note for REFB pin under INT/EXT reference modes.Go
- Added note for REFT pin under INT/EXT reference modes.Go
- Changed the maximum rating of digital input pins RESET, SCLK, SDATA, SYNC, PD, CSZ to 3.6V.Go
- Added test condition "Digital Filter Disabled" and changed "LVDS output rate" to "ADC CLK Frequency" in LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled.Go
- Added test condition "Digital Filter Disabled" and changed "LVDS output rate" to "ADC CLK Frequency" in LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled.Go
- Added note after LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled : The above LVDS timing spec is only valid when digital filters are disabled...Go
- Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled.Go
- Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled.Go
- Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled.Go
- Added a note related to EN_CUSTOM_FILT and changed formats in Table 9.Go
- Added PLL Operation Versus LVDS Timing before APPLICATION INFORMATION section Go
- Added a note link to Reg.0x38 .Go
- Changed 0xF[15] to 0xF0[15] in the description of Reg.0x42.Go
- Changed the Reg.0x46[11:8] formatting. Go
- Corrected the EN_RAMP address from 0x24 to 0x25 in the section of LVDS test patterns. Go
- Changed "Note that these bits are functional only when the GLOBAL_EN_FILTER gets set to 1" to " Note that these bits are functional only when the GLOBAL_EN_FILTER gets set to 1 and USE_FILTERn bit is set to 1” in the section of Decimation Filter,. Go
- Added a note related to EN_CUSTOM_FILT and changed formats inTable 9 .Go
- Changed Equation (5).Go
- Added register address in Table 11.Go
- Revised Figure 63 and moved the 2pF cap to the left hand side of the resistors. Go
- Added a note regarding the location of LVDS Rterm in the section of Input clock. Go
Changes from A Revision (November 2011) to B Revision
- Changed the location of OUT A and OUT B in Figure 5 and Figure 6Go
- Added Figure 45Go
- Replaced Table 9 (Decimation Filter Modes) with new Table 1 - Digital FiltersGo
- Deleted section: Synchronization PulseGo
- Added EN_HIGH_ADDRS to Table 3Go
- Moved EN_EXT_REF From: 0x0F To: 0xF0 in Table 3Go
- Added the section BIT-BYTE-WORD WISE OUTPUT. Added Figure 53 and Figure 54.Go
- Added section DIGITAL PROCESSING BLOCKSGo
- Replaced Table 5 and Table 6 with new Table 9 - Digital FiltersGo
- Changed the SYNCHRONIZATION PULSE sectionGo
- Added the External Reference Mode of Operation sectionGo
Changes from * Revision (November 2011) to A Revision