JAJSFA9E
November 2011 – April 2018
ADS5294
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
ブロック概略図
4
改訂履歴
5
概要(続き)
6
デバイス比較表
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics Dynamic Performance
8.6
Digital Characteristics
8.7
Timing Requirements
8.8
LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
8.9
LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
8.10
Serial Interface Timing Requirements
8.11
Reset Timing
8.12
LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
8.13
LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
8.14
LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
8.15
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Analog Input
9.3.2
Input Clock
9.3.3
Digital Highpass IIR Filter
9.3.4
Decimation Filter
9.3.5
Decimation Filter Equation
9.3.5.1
Pre-defined Coefficients
9.3.5.2
Custom Filter Coefficients
9.3.6
PLL Operation Versus LVDS Timing
9.3.6.1
Effect on Output Timings
9.4
Device Functional Modes
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Register Initialization
9.5.1.2
Serial Register Readout
9.5.1.3
Default States After Reset
9.6
Register Maps
9.6.1
Description Of Serial Registers
9.6.1.1
Power-Down Modes
Table 1.
Power-Down Mode Register
9.6.1.2
Low Frequency Noise Suppression Mode
Table 2.
Low Frequency Noise Suppression Mode Register
9.6.1.3
Analog Input Invert
Table 3.
Analog Input Invert Register
9.6.1.4
LVDS Test Patterns
Table 4.
LVDS Test Patterns
9.6.1.5
Bit-Byte-Word Wise Output
Table 5.
Bit-Byte-Word Wise Output
9.6.1.6
Digital Processing Blocks
9.6.1.7
Programmable Digital Gain
Table 6.
Programmable Digital Gain
9.6.1.8
Channel Averaging
Table 7.
Channel Averaging
9.6.1.9
Decimation Filter
Table 8.
Decimation Filter
9.6.1.10
Highpass Filter
Table 9.
Highpass Filter
9.6.1.11
Bit-Clock Programmability
Table 10.
Bit-Clock Programmability
9.6.1.12
Output Data Rate Control
Table 11.
Output Data Rate Control
9.6.1.13
Synchronization Pulse
Table 12.
Synchronization Pulse
9.6.1.14
External Reference Mode of Operation
9.6.1.15
Data Output Format Modes
Table 13.
Data Output Format Modes
9.6.1.16
Programmable Mapping Between Input Channels and Output Pins
Table 14.
Mapping Between Input Channels and Output Pins
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Large and Small Signal Input Bandwidth
10.2.2.2
Drive Circuit
10.2.2.3
Clock Selection
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
デバイス・サポート
13.1.1
デバイスの項目表記
13.1.1.1
仕様の定義
13.2
ドキュメントのサポート
13.2.1
関連資料
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PFP|80
MPQF049B
サーマルパッド・メカニカル・データ
PFP|80
PPTD013N
発注情報
jajsfa9e_oa
jajsfa9e_pm
9
Detailed Description