JAJSFA9E November   2011  – April 2018 ADS5294

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics Dynamic Performance
    6. 8.6  Digital Characteristics
    7. 8.7  Timing Requirements
    8. 8.8  LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled
    9. 8.9  LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled
    10. 8.10 Serial Interface Timing Requirements
    11. 8.11 Reset Timing
    12. 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled
    13. 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled
    14. 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled
    15. 8.15 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Input Clock
      3. 9.3.3 Digital Highpass IIR Filter
      4. 9.3.4 Decimation Filter
      5. 9.3.5 Decimation Filter Equation
        1. 9.3.5.1 Pre-defined Coefficients
        2. 9.3.5.2 Custom Filter Coefficients
      6. 9.3.6 PLL Operation Versus LVDS Timing
        1. 9.3.6.1 Effect on Output Timings
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
        2. 9.5.1.2 Serial Register Readout
        3. 9.5.1.3 Default States After Reset
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
        1. 9.6.1.1  Power-Down Modes
          1. Table 1. Power-Down Mode Register
        2. 9.6.1.2  Low Frequency Noise Suppression Mode
          1. Table 2. Low Frequency Noise Suppression Mode Register
        3. 9.6.1.3  Analog Input Invert
          1. Table 3. Analog Input Invert Register
        4. 9.6.1.4  LVDS Test Patterns
          1. Table 4. LVDS Test Patterns
        5. 9.6.1.5  Bit-Byte-Word Wise Output
          1. Table 5. Bit-Byte-Word Wise Output
        6. 9.6.1.6  Digital Processing Blocks
        7. 9.6.1.7  Programmable Digital Gain
          1. Table 6. Programmable Digital Gain
        8. 9.6.1.8  Channel Averaging
          1. Table 7. Channel Averaging
        9. 9.6.1.9  Decimation Filter
          1. Table 8. Decimation Filter
        10. 9.6.1.10 Highpass Filter
          1. Table 9. Highpass Filter
        11. 9.6.1.11 Bit-Clock Programmability
          1. Table 10. Bit-Clock Programmability
        12. 9.6.1.12 Output Data Rate Control
          1. Table 11. Output Data Rate Control
        13. 9.6.1.13 Synchronization Pulse
          1. Table 12. Synchronization Pulse
        14. 9.6.1.14 External Reference Mode of Operation
        15. 9.6.1.15 Data Output Format Modes
          1. Table 13. Data Output Format Modes
        16. 9.6.1.16 Programmable Mapping Between Input Channels and Output Pins
          1. Table 14. Mapping Between Input Channels and Output Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Large and Small Signal Input Bandwidth
        2. 10.2.2.2 Drive Circuit
        3. 10.2.2.3 Clock Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
        1. 13.1.1.1 仕様の定義
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.1.9 Decimation Filter

Table 8. Decimation Filter

ADDR. (HEX) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME
29 X GLOBAL_EN_FILTER
2E X X X FILTER1_COEFF_SET<2:0>
X X X FILTER1_RATE<2:0>
X ODD_TAP1
X USE_FILTER1
2F X X X FILTER2_COEFF_SET<2:0>
X X X FILTER2_RATE<2:0>
X ODD_TAP2
X USE_FILTER2
30 X X X FILTER3_COEFF_SET<2:0>
X X X FILTER3_RATE<2:0>
X ODD_TAP3
X USE_FILTER3
31 X X X FILTER4_COEFF_SET<2:0>
X X X FILTER4_RATE<2:0>
X ODD_TAP4
X USE_FILTER4
32 X X X FILTER5_COEFF_SET<2:0>
X X X FILTER5_RATE<2:0>
X ODD_TAP5
X USE_FILTER5
33 X X X FILTER6_COEFF_SET<2:0>
X X X FILTER6_RATE<2:0>
X ODD_TAP6
X USE_FILTER6
34 X X X FILTER7_COEFF_SET<2:0>
X X X FILTER7_RATE<2:0>
X ODD_TAP7
X USE_FILTER7
35 X X X FILTER8_COEFF_SET<2:0>
X X X FILTER8_RATE<2:0>
X ODD_TAP8
X USE_FILTER8

The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit signed). The filter equation is:

Equation 2. ADS5294 EQ1_yn1_las776.gif

By setting the register bit <ODD_TAPn> = 1, a 23-tap FIR is implemented:

Equation 3. ADS5294 EQ2_yn2_las776.gif

In Equation 2 and Equation 3, h0, h1 …h11 are 12-bit signed representation of the coefficients, x(n) is the input data sequence to the filter and y(n) is the filter output sequence.

A decimation filter can be introduced at the output of each channel. To enable this feature, the GLOBAL_EN_FILTER should be set to ‘1’. Setting this bit to ‘1’ increases the overall latency of each channel to 20 clock cycles irrespective of whether the filter for that particular channel has been chosen or not (using the USE_FILTER bit). The bits marked FILTERn_COEFF_SET<2:0>, FILTERn_RATE<2:0>, ODD_TAPn and USE_FILTERn represent the controls for the filter for Channel n. Note that these bits are functional only when the GLOBAL_EN_FILTER gets set to '1' and USE_FILTERn bit is set to '1'. For illustration, the controls for channel 1 are listed in Table 9:

The USE_FILTER1 bit determines whether the filter for Channel 1 is used or not. When this bit is set to ‘1’, the filter for channel 1 is enabled. When this bit is set to ‘0’, the filter for channel 1 is disabled but the channel data passes through a dummy delay so that the overall latency of channel 1 is 20 clock cycles. With the USE_FILTER1 bit set to ‘1’, the characteristics of the filter can be set by using the other sets of bits.

The ADS5294 has six sets of filter coefficients stored in memory. Each of these sets define a unique pass band in the frequency domain and contain 12 coefficients (each coefficient is 12-bit long). These 12 coefficients are used to implement either a symmetric 24-tap (even-tap) filter, or a symmetric 23-tap (odd-tap) filter. Setting the register bit ODD_TAP1 to ‘1’ enables the odd-tap configuration (the default is even tap with this bit set to ‘0’) for Channel 1. The bits FILTER1_COEFF_SET<2:0> are used to choose the required set of coefficients for Channel 1.

The passbands corresponding to of each of these filter coefficient sets is shown in Figure 56

ADS5294 flt_typs_las776.gifFigure 56. Filter Types

Coefficient Sets 1 and 2 are the most appropriate when decimation by a factor of 2 is required, whereas Coefficient Sets 3, 4, 5, and 6 are appropriate when decimation by a factor of 4 is desired. The computation rate of the filter output is set independently using the bits FILTERn_RATE<2:0>. The settings are shown in Table 9.

Table 9. Digital Filters

DECIMATION TYPE OF FILTER DATA_RATE> FILTERn_RATE FILTERn_COEFF_SET ODD_TAP USE_FILTER_CHn EN_CUSTOM_FILT
Decimate by 2 Built-in low-pass odd-tap filter (pass band = 0 to fS/4) 01 000 000 1 1 0
Built-in highpass odd-tap filter (pass band = fS/4 to fS/2 ) 01 000 001 1 1 0
Decimate by 4 Built-in lowpass even-tap filter (pass band = 0 to fS/8) 10 001 010 0 1 0
Built-in first bandpass even tap filter(pass band = fS/8 to fS/4) 10 001 011 0 1 0
Built-in second bandpass even tap filter(pass band = fS/4 to 3 fS/8) 10 001 100 0 1 0
Built-in highpass odd tap filter (pass band = 3 fS/8 to fS/2) 10 001 101 1 1 0
Decimate by 2 Custom filter (user-programmable coefficients) 01 000 000 0 and 1 1 1
Decimate by 4 Custom filter (user-programmable coefficients) 10 001 000 0 and 1 1 1
Decimate by 8 Custom filter (user-programmable coefficients) 11 100 000 0 and 1 1 1
Bypass decimation Custom filter (user-programmable coefficients) 00 011 000 0 and 1 1 1
Note: EN_CUSTOM_FILT is the D15 of register 5A (Hex) to B9 (Hex).

The choice of the odd or even tap setting, filter coefficient set, and the filter rate uniquely determines the filter to be used. In addition to the preset filter coefficients, the coefficients for each of the eight filter channels can be programmed by the user. Each of the eight channels has 12 programmable coefficients, each 12-bit long. The 96 registers with addresses from 5A (Hex) to B9 (Hex) are used to program these eight sets of 12 programmable coefficients. Registers 5A to 65 are used to program the first filter, with the first coefficient occupying the bits D11..D0 of register 5A, the second coefficient occupying the bits D11..D0 of register 5B, and so on. Similarly registers 66 (Hex) to 71 (Hex) are used to program the second filter, and so on.

When programming the filter coefficients, the D15 bit, EN_CUSTOM_FILT, of each of the 12 registers corresponding to that filter should be set to ‘1’. If the D15 bit of these 12 registers is set to ‘0’, then the preset coefficient (as programmed by FILTERn_COEFF_SET<2:0>) is used even if the bits D11..D0 get programmed. By setting or not setting the D15 bits of individual filter channels to ‘1’, some filters can be made to operate with preset coefficient sets, and some others can be made to simultaneously operate with programmed coefficient sets.