JAJSFA9E November 2011 – April 2018 ADS5294
PRODUCTION DATA.
ADDR. (HEX) | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
25 | TP_HARD_SYNC | |||||||||||||||
02 | EN_SYNC |
The SYNC pin synchronizes the data output from channels within the same chip or from channels across chips when decimation filters are used with reduced output data rate.
When the decimation filters are used (for example, the decimate-by-two filter is enabled), then, effectively, the device outputs one digital code for every two analog input samples. If the SYNC function is not enabled, then the filters are not synchronized (even within a chip) which means that one channel is sending out codes corresponding to input samples N, N + 1 and so on, while another may be sending out code corresponding to N + 1, N + 2, and so on.
To achieve synchronization, the SYNC pulse must arrive at all the ADS529x chips at the same time instant (as shown in the timing diagram of Figure 60
The ADS5294 generates an internal synchronization signal which is used to reset the internal clock dividers used by the decimation filter.
Using the SYNC signal in this way ensures that all channels will output digital codes corresponding to the same set of input samples.
SYNC Timings:
Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be written. Even EN_SYNC bit is not required.It is important for register bit TP_HARD_SYNC to be 0 for this mode to work. As shown by Figure 60, the SYNC rising edge can be positioned anywhere within the window. The width of the SYNC must be at least one clock cycle.
Note that the SYNC DOES NOT synchronize the sampling instants of the ADC across chips. All channels within a single chip sample their analog inputs simultaneously. The input clock needs to be routed to both chips with identical length to ensure that channels across two chips will sample their analog inputs simultaneously. Taking this step ensures that the input clocks arrive at both of the chips at the same time. This should be handled in the board design and routing. The SYNC pin cannot be used to synchronize the sampling instants.
In addition to the above, the SYNC also synchronizes the RAMP test patterns across channels. In order to synchronize the test patterns, TP_HARD_SYNC must be set as '1'. Setting TP_HARD_SYNC = 1 actually disables the sync of the filters.