SLAU847 User guide

Table 22-21 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 22-21 should be considered as reserved locations and the register contents should not be modified.

Table 22-21 I2C Registers

Offset	Acronym	Register Name	Section
800h	PWREN	Power enable	Section 22.3.1
804h	RSTCTL	Reset Control	Section 22.3.2
808h	CLKCFG	Peripheral Clock Configuration Register	Section 22.3.3
814h	STAT	Status Register	Section 22.3.4
1000h	CLKDIV	Clock Divider	Section 22.3.5
1004h	CLKSEL	Clock Select for Ultra Low Power peripherals	Section 22.3.6
1018h	PDBGCTL	Peripheral Debug Control	Section 22.3.7
1020h	IIDX	Interrupt index	Section 22.3.8
1028h	IMASK	Interrupt mask	Section 22.3.9
1030h	RIS	Raw interrupt status	Section 22.3.10
1038h	MIS	Masked interrupt status	Section 22.3.11
1040h	ISET	Interrupt set	Section 22.3.12
1048h	ICLR	Interrupt clear	Section 22.3.13
1050h	IIDX	Interrupt index	Section 22.3.14
1058h	IMASK	Interrupt mask	Section 22.3.15
1060h	RIS	Raw interrupt status	Section 22.3.16
1068h	MIS	Masked interrupt status	Section 22.3.17
1070h	ISET	Interrupt set	Section 22.3.18
1078h	ICLR	Interrupt clear	Section 22.3.19
1080h	IIDX	Interrupt index	Section 22.3.20
1088h	IMASK	Interrupt mask	Section 22.3.21
1090h	RIS	Raw interrupt status	Section 22.3.22
1098h	MIS	Masked interrupt status	Section 22.3.23
10A0h	ISET	Interrupt set	Section 22.3.24
10A8h	ICLR	Interrupt clear	Section 22.3.25
10E0h	EVT_MODE	Event Mode	Section 22.3.26
10E4h	INTCTL	Interrupt control register	Section 22.3.27
10FCh	DESC	Module Description	Section 22.3.28
1200h	GFCTL	I2C Glitch Filter Control	Section 22.3.29
1204h	TIMEOUT_CTL	I2C Timeout Count Control Register	Section 22.3.30
1208h	TIMEOUT_CNT	I2C Timeout Count Register	Section 22.3.31
1210h	CSA	I2C Controller Target Address Register	Section 22.3.32
1214h	CCTR	I2C Controller Control Register	Section 22.3.33
1218h	CSR	I2C Controller Status Register	Section 22.3.34
121Ch	CRXDATA	I2C Controller RXData	Section 22.3.35
1220h	CTXDATA	I2C Controller TXData	Section 22.3.36
1224h	CTPR	I2C Controller Timer Period	Section 22.3.37
1228h	CCR	I2C Controller Configuration	Section 22.3.38
1234h	CBMON	I2C Controller Bus Monitor	Section 22.3.39
1238h	CFIFOCTL	I2C Controller FIFO Control	Section 22.3.40
123Ch	CFIFOSR	I2C Controller FIFO Status Register	Section 22.3.41
1240h	_I2CPECCTL	I2C Controller PEC control register	Section 22.3.42
1244h	_PECSR	I2C Controller PEC status register	Section 22.3.43
1250h	TOAR	I2C Target Own Address	Section 22.3.44
1254h	TOAR2	I2C Target Own Address 2	Section 22.3.45
1258h	TCTR	I2C Target Control Register	Section 22.3.46
125Ch	TSR	I2C Target Status Register	Section 22.3.47
1260h	TRXDATA	I2C Target RXData	Section 22.3.48
1264h	TTXDATA	I2C Target TXData	Section 22.3.49
1268h	TACKCTL	I2C Target ACK Control	Section 22.3.50
126Ch	TFIFOCTL	I2C Target FIFO Control	Section 22.3.51
1270h	TFIFOSR	I2C Target FIFO Status Register	Section 22.3.52
1274h	_PECCTL	I2C Target PEC control register	Section 22.3.53
1278h	_PECSR	I2C Target PEC status register	Section 22.3.54

Complex bit access types are encoded to fit into small table cells. Table 22-22 shows the codes that are used for access types in this section.

Table 22-22 I2C Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
WK	W K	Write Write protected by a key
Reset or Default Value
-n		Value after reset or the default value

22.3.1 PWREN Register (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Table 22-23.

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Register to control the power state

Table 22-23 PWREN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	KEY	W	0h	KEY to allow Power State Change 26h = KEY to allow write access to this register
23-1	RESERVED	R	0h
0	ENABLE	R/WK	0h	Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power

22.3.2 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Table 22-24.

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Register to control reset assertion and de-assertion

Table 22-24 RSTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	KEY	W	0h	Unlock key B1h = KEY to allow write access to this register
23-2	RESERVED	R	0h
1	RESETSTKYCLR	WK	0h	Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit
0	RESETASSERT	WK	0h	Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset

22.3.3 CLKCFG Register (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Table 22-25.

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Peripheral Clock Configuration Register

Table 22-25 CLKCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	KEY	W	0h	KEY to Allow State Change -- 0xA9 A9h = key value to allow change field of GPRCM
23-9	RESERVED	R	0h
8	BLOCKASYNC	R/W	0h	Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0h = Not block async clock request 1h = Block async clock request
7-0	RESERVED	R	0h

22.3.4 STAT Register (Offset = 814h) [Reset = 00000000h]

STAT is shown in Table 22-26.

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peripheral enable and reset status

Table 22-26 STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h
16	RESETSTKY	R	0h	This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear
15-0	RESERVED	R	0h

22.3.5 CLKDIV Register (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Table 22-27.

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This register is used to specify module-specific divide ratio of the functional clock

Table 22-27 CLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h
2-0	RATIO	R/W	0h	Selects divide ratio of module clock 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8

22.3.6 CLKSEL Register (Offset = 1004h) [Reset = 00000000h]

CLKSEL is shown in Table 22-28.

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Clock source selection.

Table 22-28 CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	BUSCLK_SEL	R/W	0h	Selects BUSCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source
2	MFCLK_SEL	R/W	0h	Selects MFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source
1-0	RESERVED	R	0h

22.3.7 PDBGCTL Register (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Table 22-29.

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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Table 22-29 PDBGCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h
1	SOFT	R/W	1h	Soft halt boundary control. This function is only available, if FREE is set to 'STOP' 0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0	FREE	R/W	1h	Free run control 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input

22.3.8 IIDX Register (Offset = 1020h) [Reset = 00000000h] (CPU_INT)

IIDX is shown in Table 22-30.

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This register provides the highest priority enabled interrupt index.

Table 22-30 IIDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	STAT	R	0h	I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller data received 02h = Controller data transmitted 03h = Controller receive FIFO Trigger Level 04h = Controller transmit FIFO Trigger level 5h = RX FIFO FULL Event/interrupt pending 6h = Transmit FIFO/Buffer Empty Event/interrupt pending 08h = Address/Data NACK 09h = Start Event 0Ah = Stop Event 0Bh = Arbitration Lost Ch = DMA DONE on Channel TX Dh = DMA DONE on Channel RX Eh = Controller PEC Receive Error Event Fh = Timeout A Event 10h = Timeout B Event 11h = Target Data Event 12h = Target Data Event 13h = Target receive FIFO Trigger Level 14h = Target transmit FIFO Trigger level 15h = RX FIFO FULL Event/interrupt pending 16h = Transmit FIFO/Buffer Empty Event/interrupt pending 17h = Start Event 18h = Stop Event 19h = General Call Event 1Ah = DMA DONE on Channel TX 1Bh = DMA DONE on Channel RX 1Ch = Target PEC receive error event 1Dh = Target TX FIFO underflow 1Eh = Target RX FIFO overflow event 1Fh = Target arbitration lost event 20h = Interrupt overflow event

22.3.9 IMASK Register (Offset = 1028h) [Reset = 00000000h] (CPU_INT)

IMASK is shown in Table 22-31.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 22-31 IMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INTR_OVFL	R/W	0h	Interrupt Overflow Interrupt Mask 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
30	TARBLOST	R/W	0h	Target Arbitration Lost 0h = Clear Set Interrupt Mask 1h = Set Interrupt Mask
29	TRX_OVFL	R/W	0h	Target RX FIFO overflow 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
28	TTX_UNFL	R/W	0h	Target TX FIFO underflow 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
27	TPEC_RX_ERR	R/W	0h	Target RX Pec Error Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
26	TDMA_DONE_RX	R/W	0h	Target DMA Done on Event Channel RX 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
25	TDMA_DONE_TX	R/W	0h	Target DMA Done on Event Channel TX 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
24	TGENCALL	R/W	0h	General Call Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
23	TSTOP	R/W	0h	Stop Condition Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
22	TSTART	R/W	0h	Start Condition Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
21	TTXEMPTY	R/W	0h	Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
20	TRXFIFOFULL	R/W	0h	RXFIFO full event. This interrupt is set if an Target RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
19	TTXFIFOTRG	R/W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
18	TRXFIFOTRG	R/W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
17	TTXDONE	R/W	0h	Target Transmit Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
16	TRXDONE	R/W	0h	Target Receive Data Interrupt Signals that a byte has been received 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
15	TIMEOUTB	R/W	0h	Timeout B Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
14	TIMEOUTA	R/W	0h	Timeout A Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
13	CPEC_RX_ERR	R/W	0h	Controller RX Pec Error Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
12	CDMA_DONE_RX	R/W	0h	DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask
11	CDMA_DONE_TX	R/W	0h	DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask
10	CARBLOST	R/W	0h	Arbitration Lost Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
9	CSTOP	R/W	0h	STOP Detection Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
8	CSTART	R/W	0h	START Detection Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
7	CNACK	R/W	0h	Address/Data NACK Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
6	RESERVED	R	0h
5	CTXEMPTY	R/W	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
4	CRXFIFOFULL	R/W	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
3	CTXFIFOTRG	R/W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	CRXFIFOTRG	R/W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXDONE	R/W	0h	Controller Transmit Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXDONE	R/W	0h	Controller Receive Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.10 RIS Register (Offset = 1030h) [Reset = 00000000h] (CPU_INT)

RIS is shown in Table 22-32.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 22-32 RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INTR_OVFL	R	0h	Interrupt overflow interrupt It is set when CSTART or CSTOP interrupts overflow i.e. occur twice without being serviced 0h = Interrupt did not occur 1h = Interrupt occured
30	TARBLOST	R	0 h	Target Arbitration Lost 0h = Interrupt did not occur 1h = Interrupt occured
29	TRX_OVFL	R	0h	Target RX FIFO overflow 0h = Interrupt did not occur 1h = Interrupt Occured
28	TTX_UNFL	R	0h	Target TX FIFO underflow 0h = Interrupt did not occur 1h = Interrupt occured
27	TPEC_RX_ERR	R	0h	Target RX Pec Error Interrupt 0h = Interrupt did not occur 1h = Interrupt ocuured
26	TDMA_DONE_RX	R	0h	DMA Done on Event Channel RX 0h = Clear interrupt 1h = Set interrupt
25	TDMA_DONE_TX	R	0h	DMA Done on Event Channel TX 0h = Clear interrupt 1h = Set interrupt
24	TGENCALL	R	0h	General Call Interrupt 0h = Clear Interrupt Mask 1h = Interrupt occured
23	TSTOP	R	0h	Stop Condition Interrupt 0h = Clear Interrupt 1h = Set interrupt
22	TSTART	R	0h	Start Condition Interrupt 0h = Clear interrupt 1h = Set Interrupt
21	TTXEMPTY	R	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Interrupt occured
20	TRXFIFOFULL	R	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Interrupt occured
19	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Interrupt occured
18	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Interrupt occured
17	TTXDONE	R	0h	Target Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
16	TRXDONE	R	0h	Target Receive Data Interrupt Signals that a byte has been received 0h = Interrupt did not occur 1h = Interrupt occured
15	TIMEOUTB	R	0h	Timeout B Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
14	TIMEOUTA	R	0h	Timeout A Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
13	CPEC_RX_ERR	R	0h	Controller RX Pec Error Interrupt 0h = Interrupt did not occur 1h = Interrupt Occured
12	CDMA_DONE_RX	R	0h	DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Interrupt occured
11	CDMA_DONE_TX	R	0h	DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Interrupt occured
10	CARBLOST	R	0h	Arbitration Lost Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
9	CSTOP	R	0h	STOP Detection Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
8	CSTART	R	0h	START Detection Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
7	CNACK	R	0h	Address/Data NACK Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
6	RESERVED	R	0h
5	CTXEMPTY	R	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Interrupt occured
4	CRXFIFOFULL	R	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Interrupt did not occur 1h = Interrupt occured
3	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Interrupt occured
2	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Interrupt occured
1	CTXDONE	R	0h	Controller Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
0	CRXDONE	R	0h	Controller Receive Transaction completed Interrupt 0h = Interrupt did not occur 1h = Interrupt occured

22.3.11 MIS Register (Offset = 1038h) [Reset = 00000000h] (CPU_INT)

MIS is shown in Table 22-33.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 22-33 MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INTR_OVFL	R	0h	Interrupt overflow 0h = Interrupt did not occur 1h = Interrupt occured
30	TARBLOST	R	0h	Target Arbitration Lost 0h = Clear interrupt mask 1h = Set interrupt mask
29	TRX_OVFL	R	0h	Target RX FIFO overflow 0h = Clear interrupt mask 1h = Set interrupt mask
28	TTX_UNFL	R	0h	Target TX FIFO underflow 0h = Clear interrupt mask 1h = Set interrupt mask
27	TPEC_RX_ERR	R	0h	Target RX Pec Error Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask
26	TDMA_DONE_RX	R	0h	DMA Done on Event Channel RX 0h = Clear MIS 1h = Set MIS
25	TDMA_DONE_TX	R	0h	DMA Done on Event Channel TX 0h = Clear MIS 1h = Set MIS
24	TGENCALL	R	0h	General Call Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
23	TSTOP	R	0h	Target STOP Detection Interrupt 0h = Clear MIS 1h = Set MIS
22	TSTART	R	0h	Target START Detection Interrupt 0h = Clear MIS 1h = Set MIS
21	TTXEMPTY	R	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Interrupt occured
20	TRXFIFOFULL	R	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Interrupt occured
19	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Interrupt occured
18	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Interrupt occured
17	TTXDONE	R	0h	Target Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
16	TRXDONE	R	0h	Target Receive Data Interrupt Signals that a byte has been received 0h = Interrupt did not occur 1h = Interrupt occured
15	TIMEOUTB	R	0h	Timeout B Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask
14	TIMEOUTA	R	0h	Timeout A Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
13	CPEC_RX_ERR	R	0h	Controller RX Pec Error Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask
12	CDMA_DONE_RX	R	0h	DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Interrupt occured
11	CDMA_DONE_TX	R	0h	DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Interrupt occured
10	CARBLOST	R	0h	Arbitration Lost Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
9	CSTOP	R	0h	STOP Detection Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
8	CSTART	R	0h	START Detection Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
7	CNACK	R	0h	Address/Data NACK Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
6	RESERVED	R	0h
5	CTXEMPTY	R	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Interrupt occured
4	CRXFIFOFULL	R	0h	RXFIFO full event. This interrupt is set if the RX FIFO is full. 0h = Interrupt did not occur 1h = Interrupt occured
3	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Interrupt occured
2	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Interrupt occured
1	CTXDONE	R	0h	Controller Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Interrupt occured
0	CRXDONE	R	0h	Controller Receive Data Interrupt 0h = Interrupt did not occur 1h = Interrupt occured

22.3.12 ISET Register (Offset = 1040h) [Reset = 00000000h] (CPU_INT)

ISET is shown in Table 22-34.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 22-34 ISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INTR_OVFL	W	0h	Interrupt overflow 0h = No effect 1h = Set interrupt
30	TARBLOST	W	0h	Target Arbitration Lost 0h = Writing 0 has no effect 1h = Set interrupt
29	TRX_OVFL	W	0h	Target RX FIFO overflow 0h = Writing 0 has no effect 1h = Set interrupt
28	TTX_UNFL	W	0h	Target TX FIFO underflow 0h = Writing 0 has no effect 1h = Set interrupt
27	TPEC_RX_ERR	W	0h	Target RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Set interrupt
26	TDMA_DONE_RX	W	0h	DMA Done on Event Channel RX 0h = Writing 0 has no effect 1h = Set interrupt
25	TDMA_DONE_TX	W	0h	DMA Done on Event Channel TX 0h = Writing 0 has no effect 1h = Set interrupt
24	TGENCALL	W	0h	General Call Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
23	TSTOP	W	0h	Stop Condition Interrupt 0h = Writing 0 has no effect 1h = Set interrupt
22	TSTART	W	0h	Start Condition Interrupt 0h = Writing 0 has no effect 1h = Set interrupt
21	TTXEMPTY	W	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt
20	TRXFIFOFULL	W	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt
19	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt
18	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt
17	TTXDONE	W	0h	Target Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
16	TRXDONE	W	0h	Target Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt
15	TIMEOUTB	W	0h	Timeout B Interrupt 0h = Writing 0 has no effect 1h = Set interrupt
14	TIMEOUTA	W	0h	Timeout A interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
13	CPEC_RX_ERR	W	0h	Controller RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Set interrupt
12	CDMA_DONE_RX	W	0h	DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt
11	CDMA_DONE_TX	W	0h	DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt
10	CARBLOST	W	0h	Arbitration Lost Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
9	CSTOP	W	0h	STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
8	CSTART	W	0h	START Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
7	CNACK	W	0h	Address/Data NACK Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
6	RESERVED	R	0h
5	CTXEMPTY	W	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt
4	CRXFIFOFULL	W	0h	RXFIFO full event. 0h = Writing 0 has no effect 1h = Set Interrupt
3	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt
2	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt
1	CTXDONE	W	0h	Controller Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt
0	CRXDONE	W	0h	Controller Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt

22.3.13 ICLR Register (Offset = 1048h) [Reset = 00000000h] (CPU_INT)

ICLR is shown in Table 22-35.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-35 ICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	INTR_OVFL	W	0h	Interrupt overflow 0h = No effect 1h = Clear interrupt
30	TARBLOST	W	0h	Target Arbitration Lost 0h = Writing 0 has no effect 1h = Clear Interrupt
29	TRX_OVFL	W	0h	Target RX FIFO overflow 0h = Writing 0 has no effect 1h = Clear Interrupt
28	TTX_UNFL	W	0h	Target TX FIFO underflow 0h = Writing 0 has no effect 1h = Clear Interrupt
27	TPEC_RX_ERR	W	0h	Target RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
26	TDMA_DONE_RX	W	0h	DMA Done on Event Channel RX 0h = Writing 0 has no effect 1h = Clear interrupt
25	TDMA_DONE_TX	W	0h	DMA Done on Event Channel TX 0h = Writing 0 has no effect 1h = Clear interrupt
24	TGENCALL	W	0h	General Call Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
23	TSTOP	W	0h	Target STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Clear interrupt
22	TSTART	W	0h	Target START Detection Interrupt 0h = Writing 0 has no effect 1h = Clear interrupt
21	TTXEMPTY	W	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Clear Interrupt
20	TRXFIFOFULL	W	0h	RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Clear Interrupt
19	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Clear Interrupt
18	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Clear Interrupt
17	TTXDONE	W	0h	Target Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
16	TRXDONE	W	0h	Target Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Clear Interrupt
15	TIMEOUTB	W	0h	Timeout B Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
14	TIMEOUTA	W	0h	Timeout A interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
13	CPEC_RX_ERR	W	0h	Controller RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
12	CDMA_DONE_RX	W	0h	DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Clear Interrupt
11	CDMA_DONE_TX	W	0h	DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Clear Interrupt
10	CARBLOST	W	0h	Arbitration Lost Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
9	CSTOP	W	0h	STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
8	CSTART	W	0h	START Detection Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
7	CNACK	W	0h	Address/Data NACK Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
6	RESERVED	R	0h
5	CTXEMPTY	W	0h	Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Clear Interrupt
4	CRXFIFOFULL	W	0h	RXFIFO full event. 0h = Writing 0 has no effect 1h = Clear Interrupt
3	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Clear Interrupt
2	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Clear Interrupt
1	CTXDONE	W	0h	Controller Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt
0	CRXDONE	W	0h	Controller Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Clear Interrupt

22.3.14 IIDX Register (Offset = 1050h) [Reset = 00000000h] (DMA_TRIG1)

IIDX is shown in Table 22-36.

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This register provides the highest priority enabled interrupt index.

Table 22-36 IIDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	STAT	R	0h	I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller receive FIFO Trigger Level 02h = Controller transmit FIFO Trigger level 03h = Target receive FIFO Trigger Level 04h = Target transmit FIFO Trigger level

22.3.15 IMASK Register (Offset = 1058h) [Reset = 00000000h] (DMA_TRIG1)

IMASK is shown in Table 22-37.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 22-37 IMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R/W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R/W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R/W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R/W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.16 RIS Register (Offset = 1060h) [Reset = 00000000h] (DMA_TRIG1)

RIS is shown in Table 22-38.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 22-38 RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.17 MIS Register (Offset = 1068h) [Reset = 00000000h] (DMA_TRIG1)

MIS is shown in Table 22-39.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 22-39 MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.18 ISET Register (Offset = 1070h) [Reset = 00000000h] (DMA_TRIG1)

ISET is shown in Table 22-40.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 22-40 ISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.19 ICLR Register (Offset = 1078h) [Reset = 00000000h] (DMA_TRIG1)

ICLR is shown in Table 22-41.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-41 ICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.20 IIDX Register (Offset = 1080h) [Reset = 00000000h] (DMA_TRIG0)

IIDX is shown in Table 22-42.

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This register provides the highest priority enabled interrupt index.

Table 22-42 IIDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	STAT	R	0h	I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller receive FIFO Trigger Level 02h = Controller transmit FIFO Trigger level 03h = Target receive FIFO Trigger Level 04h = Target transmit FIFO Trigger level

22.3.21 IMASK Register (Offset = 1088h) [Reset = 00000000h] (DMA_TRIG0)

IMASK is shown in Table 22-43.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 22-43 IMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R/W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R/W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R/W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R/W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.22 RIS Register (Offset = 1090h) [Reset = 00000000h] (DMA_TRIG0)

RIS is shown in Table 22-44.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 22-44 RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.23 MIS Register (Offset = 1098h) [Reset = 00000000h] (DMA_TRIG0)

MIS is shown in Table 22-45.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 22-45 MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	R	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	R	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	R	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	R	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.24 ISET Register (Offset = 10A0h) [Reset = 00000000h] (DMA_TRIG0)

ISET is shown in Table 22-46.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 22-46 ISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.25 ICLR Register (Offset = 10A8h) [Reset = 00000000h] (DMA_TRIG0)

ICLR is shown in Table 22-47.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-47 ICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	TTXFIFOTRG	W	0h	Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
2	TRXFIFOTRG	W	0h	Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
1	CTXFIFOTRG	W	0h	Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask
0	CRXFIFOTRG	W	0h	Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask

22.3.26 EVT_MODE Register (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Table 22-48.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Table 22-48 EVT_MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h
5-4	EVT2_CFG	R	2h	Event line mode select for event corresponding to none.DMA_TRIG0 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2	INT1_CFG	R	2h	Event line mode select for event corresponding to none.DMA_TRIG1 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0	INT0_CFG	R	1h	Event line mode select for event corresponding to none.CPU_INT 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

22.3.27 INTCTL Register (Offset = 10E4h) [Reset = 00000000h]

INTCTL is shown in Table 22-49.

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Interrupt control register

Table 22-49 INTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h
0	INTEVAL	W	0h	Writing a 1 to this field re-evaluates the interrupt sources. 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS.

22.3.28 DESC Register (Offset = 10FCh) [Reset = 00000000h]

DESC is shown in Table 22-50.

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This register identifies the peripheral and its exact version.

Table 22-50 DESC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MODULEID	R	1511h	Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0h = Smallest value FFFFh = Highest possible value
15-12	FEATUREVER	R	0h	Feature Set for the module instance 0h = Smallest value Fh = Highest possible value
11-8	INSTNUM	R	0h	Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0h = Smallest value Fh = Highest possible value
7-4	MAJREV	R	1h	Major rev of the IP 0h = Smallest value Fh = Highest possible value
3-0	MINREV	R	0h	Minor rev of the IP 0h = Smallest value Fh = Highest possible value

22.3.29 GFCTL Register (Offset = 1200h) [Reset = 00000000h]

GFCTL is shown in Table 22-51.

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This register controls the glitch filter on the SCL and SDA lines

Table 22-51 GFCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h
11	CHAIN	R/W	1h	Analog and digital noise filters chaining enable. 0h = When 0, chaining is disabled and only digital filter output is available to IP logic for oversampling 1h = When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for oversampling
10-9	AGFSEL	R/W	3h	Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0h = Pulses shorter then 5ns length are filtered. 1h = Pulses shorter then 10ns length are filtered. 2h = Pulses shorter then 25ns length are filtered. 3h = Pulses shorter then 50ns length are filtered.
8	AGFEN	R/W	1h	Analog Glitch Suppression Enable 0h = Analog Glitch Filter disable 1h = Analog Glitch Filter enable
7-3	RESERVED	R	0h
2-0	DGFSEL	R/W	0h	Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0h = Bypass 1h = 1 clock 2h = 2 clocks 3h = 3 clocks 4h = 4 clocks 5h = 8 clocks 6h = 16 clocks 7h = 31 clocks

22.3.30 TIMEOUT_CTL Register (Offset = 1204h) [Reset = 00020002h]

TIMEOUT_CTL is shown in Table 22-52.

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This register contains controls for Timeout Counters A and B

Table 22-52 TIMEOUT_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TCNTBEN	R/W	0h	Timeout Counter B Enable 0h = Disable Timeout Counter B 1h = Enable Timeout Counter B
30-24	RESERVED	R	0h
23-16	TCNTLB	R/W	2h	Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0h = Smallest possible value FFh = Highest possible value
15	TCNTAEN	R/W	0h	Timeout Counter A Enable 0h = Disable Timeout Counter B 1h = Enable Timeout Counter B
14-8	RESERVED	R	0h
7-0	TCNTLA	R/W	2h	Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0h = Smallest Value FFh = Highest possible value

22.3.31 TIMEOUT_CNT Register (Offset = 1208h) [Reset = 00020002h]

TIMEOUT_CNT is shown in Table 22-53.

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This register contains the upper 8 bits of a 12-bit current counter values for counter A and B. The lower four bits of the counter are not user visible and are always 0h.

Table 22-53 TIMEOUT_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h
23-16	TCNTB	R	2h	Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0h = Smallest Value FFh = Highest possible value
15-8	RESERVED	R	0h
7-0	TCNTA	R	2h	Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0h = Smallest Value FFh = Highest possible value

22.3.32 CSA Register (Offset = 1210h) [Reset = 00000000h]

CSA is shown in Table 22-54.

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I2C Controller Target Address Register

Table 22-54 CSA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	CMODE	R/W	0h	This bit selects the adressing mode to be used in Controller mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0h = 7-bit addressing mode 1h = 10-bit addressing mode
14-11	RESERVED	R	0h
10-1	TADDR	R/W	0h	I2C Target Address This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0h = Smallest value 3FFh = Highest possible value
0	DIR	R/W	0h	Receive/Send The DIR bit specifies if the next Controller operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0h = The Controller is in transmit mode. 1h = The Controller is in receive mode.

22.3.33 CCTR Register (Offset = 1214h) [Reset = 00000000h]

CCTR is shown in Table 22-55.

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This control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the I2C Controller Target Address (MSA) register is written with the desired address, the RS bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an byte transaction completed interrupt becomes active and the data may be read from the MRXDATA register. When the I2C module operates in Controller receiver mode, a set ACK bit causes the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the Target transmitter.

Table 22-55 CCTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h
27-16	CBLEN	R/W	0h	I2C transaction length This field contains the programmed length of bytes of the Transaction. 0h = Smallest value FFFh = Highest possible value
15-6	RESERVED	R	0h
5	RD_ON_TXEMPTY	R/W	0h	Read on TX Empty 0h = No special behavior 1h = When 1 the Controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to Read in the MSA then this bit is ignored. The Start must be set in the MCTR for proper I2C protocol. The Controller will first send the Start Condition, I2C Address with R/W bit set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in MTCR and MSA without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around.
4	CACKOEN	R/W	0h	Controller ACK overrride Enable 0h = No special behavior 1h = When 1 and the Controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the MCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop.
3	ACK	R/W	0h	Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. 0h = The last received data byte of a transaction is not acknowledged automatically by the Controller. 1h = The last received data byte of a transaction is acknowledged automatically by the Controller.
2	STOP	R/W	0h	Generate STOP 0h = The controller does not generate the STOP condition. 1h = The controller generates the STOP condition.
1	START	R/W	0h	Generate START 0h = The controller does not generate the START condition. 1h = The controller generates the START or repeated START condition.
0	BURSTRUN	R/W	0h	I2C Controller Enable and start transaction 0h = In standard mode, this encoding means the Controller is unable to transmit or receive data. 1h = The Controller is able to transmit or receive data.

22.3.34 CSR Register (Offset = 1218h) [Reset = 00000000h]

CSR is shown in Table 22-56.

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The status register indicates the state of the I2C bus controller.

Table 22-56 CSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h
27-16	CBCNT	R	0h	I2C Controller Transaction Count This field contains the current count-down value of the transaction. 0h = Smallest value FFFh = Highest possible value
15-7	RESERVED	R	0h
6	BUSBSY	R	0h	I2C Bus is Busy Controller State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0h = The I2C bus is idle. 1h = 'This Status bit is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE bit is low. Note that the Controller State Machine will wait until this bit is cleared before starting an I2C transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
5	IDLE	R	1h	I2C Idle 0h = The I2C controller is not idle. 1h = The I2C controller is idle.
4	ARBLST	R	0h	Arbitration Lost 0h = The I2C controller won arbitration. 1h = The I2C controller lost arbitration.
3	DATACK	R	0h	Acknowledge Data 0h = The transmitted data was acknowledged 1h = The transmitted data was not acknowledged.
2	ADRACK	R	0h	Acknowledge Address 0h = The transmitted address was acknowledged 1h = The transmitted address was not acknowledged.
1	ERR	R	0h	Error The error can be from the Target address not being acknowledged or the transmit data not being acknowledged. 0h = No error was detected on the last operation. 1h = An error occurred on the last operation.
0	BUSY	R	0h	I2C Controller FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0h = The controller is idle. 1h = The controller is busy.

22.3.35 CRXDATA Register (Offset = 121Ch) [Reset = 00000000h]

CRXDATA is shown in Table 22-57.

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I2C Controller RX FIFO Read Data Byte
This field contains the current byte being read in the RX FIFO stack.
If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Table 22-57 CRXDATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	VALUE	R	0h	Received Data. This field contains the last received data. 0h = Smallest value FFh = Highest possible value

22.3.36 CTXDATA Register (Offset = 1220h) [Reset = 00000000h]

CTXDATA is shown in Table 22-58.

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I2C Controller Transmit Data Register.
This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).

Table 22-58 CTXDATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	VALUE	R/W	0h	Transmit Data This byte contains the data to be transferred during the next transaction. 0h = Smallest value FFh = Highest possible value

22.3.37 CTPR Register (Offset = 1224h) [Reset = 00000001h]

CTPR is shown in Table 22-59.

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This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode.

Table 22-59 CTPR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h
6-0	TPR	R/W	1h	Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) × (SCL_LP + SCL_HP ) × INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0h = Smallest value 7Fh = Highest possible value

22.3.38 CCR Register (Offset = 1228h) [Reset = 00000000h]

CCR is shown in Table 22-60.

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Controller configuration register

Table 22-60 CCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h
8	LPBK	R/W	0h	I2C Loopback 0h = Normal operation. 1h = The controller in a test mode loopback configuration.
7-3	RESERVED	R	0h
2	CLKSTRETCH	R/W	0h	Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0h = Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached. 1h = Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching.
1	MCTL	R/W	0h	MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0h = Disable MultiController mode. 1h = Enable MultiController mode.
0	ACTIVE	R/W	0h	Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0h = Disables the I2C Controller operation. 1h = Enables the I2C Controller operation.

22.3.39 CBMON Register (Offset = 1234h) [Reset = 00000003h]

CBMON is shown in Table 22-61.

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This register is used to determine the SCL and SDA signal status.

Table 22-61 CBMON Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h
1	SDA	R	1h	I2C SDA Status 0h = The I2CSDA signal is low. 1h = The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations.
0	SCL	R	1h	I2C SCL Status 0h = The I2CSCL signal is low. 1h = The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations.

22.3.40 CFIFOCTL Register (Offset = 1238h) [Reset = 00000000h]

CFIFOCTL is shown in Table 22-62.

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I2C Controller FIFO Control

Table 22-62 CFIFOCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	RXFLUSH	R/W	0h	RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO
14-11	RESERVED	R	0h
10-8	RXTRIG	R/W	0h	RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0h = Trigger when RX FIFO contains >= 1 byte 1h = Trigger when RX FIFO contains >= 2 byte 2h = Trigger when RX FIFO contains >= 3 byte 3h = Trigger when RX FIFO contains >= 4 byte 4h = Trigger when RX FIFO contains >= 5 byte 5h = Trigger when RX FIFO contains >= 6 byte 6h = Trigger when RX FIFO contains >= 7 byte 7h = Trigger when RX FIFO contains >= 8 byte
7	TXFLUSH	R/W	0h	TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO
6-3	RESERVED	R	0h
2-0	TXTRIG	R/W	0h	TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0h = Trigger when the TX FIFO is empty. 1h = Trigger when TX FIFO contains ≤ 1 byte 2h = Trigger when TX FIFO contains ≤ 2 byte 3h = Trigger when TX FIFO contains ≤ 3 byte 4h = Trigger when TX FIFO contains ≤ 4 byte 5h = Trigger when TX FIFO contains ≤ 5 byte 6h = Trigger when TX FIFO contains ≤ 6 byte 7h = Trigger when TX FIFO contains ≤ 7 byte

22.3.41 CFIFOSR Register (Offset = 123Ch) [Reset = 00000800h]

CFIFOSR is shown in Table 22-63.

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I2C Controller FIFO Status Register
Note: this Register should only be read when BUSY is 0

Table 22-63 CFIFOSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	TXFLUSH	R	0h	TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active
14-12	RESERVED	R	0h
11-8	TXFIFOCNT	R	8h	Number of Bytes which could be put into the TX FIFO 0h = Smallest value 8h = Highest possible value
7	RXFLUSH	R	0h	RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active
6-4	RESERVED	R	0h
3-0	RXFIFOCNT	R	0h	Number of Bytes which could be read from the RX FIFO 0h = Smallest value 8h = Highest possible value

22.3.42 _I2CPECCTL Register (Offset = 1240h) [Reset = 00000000h]

_I2CPECCTL is shown in Table 22-64.

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I2C Controller PEC Control Register

Table 22-64 _I2CPECCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h
12	PECEN	R/W	0h	PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0h = PEC is disabled in Controller mode 1h = PEC is enabled in Controller mode
11-9	RESERVED	R	0h
8-0	PECCNT	R/W	0h	PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Controller use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Target Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the Controller_I2CPECCTL Register will clear the current PEC Byte Count in the Controller State Machine. 0h = Minimum Value 1FFh = Maximum Value

22.3.43 _PECSR Register (Offset = 1244h) [Reset = 00000000h]

_PECSR is shown in Table 22-65.

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Controller PEC Status Register

Table 22-65 _PECSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h
17	PECSTS_ERROR	R	0h	This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0h = Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 1h = Indicates if a PEC check error occurred in the transaction that occurred before the last Stop
16	PECSTS_CHECK	R	0h	This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0h = Indicates PEC was not checked in the transaction that occurred before the last Stop 1h = Indicates if the PEC was checked in the transaction that occurred before the last Stop
15-9	RESERVED	R	0h
8-0	PECBYTECNT	R	0h	PEC Byte Count This is the current PEC Byte Count of the Controller State Machine. 0h = Minimum Value 1FFh = Maximum Value

22.3.44 TOAR Register (Offset = 1250h) [Reset = 00004000h]

TOAR is shown in Table 22-66.

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This register consists of seven address bits that identify the I2C device on the I2C bus.

Table 22-66 TOAR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	TMODE	R/W	0h	This bit selects the adressing mode to be used in Target mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0h = Enable 7-bit addressing 1h = Enable 10-bit addressing
14	OAREN	R/W	1h	I2C Target Own Address Enable 0h = Disable OAR address 1h = Enable OAR address
13-10	RESERVED	R	0h
9-0	OAR	R/W	0h	I2C Target Own Address: This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0h = Smallest value 3FFh = Highest possible value

22.3.45 TOAR2 Register (Offset = 1254h) [Reset = 00000000h]

TOAR2 is shown in Table 22-67.

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This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus.

Table 22-67 TOAR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h
22-16	OAR2_MASK	R/W	0h	I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address. The bits with value ‘1’ in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a don’t care. 0h = Minimum Value 7Fh = Maximum Value
15-8	RESERVED	R	0h
7	OAR2EN	R/W	0h	I2C Target Own Address 2 Enable 0h = The alternate address is disabled. 1h = Enables the use of the alternate address in the OAR2 field.
6-0	OAR2	R/W	0h	I2C Target Own Address 2 This field specifies the alternate OAR2 address. 0h = Smallest value 7Fh = Highest possible value

22.3.46 TCTR Register (Offset = 1258h) [Reset = 00000404h]

TCTR is shown in Table 22-68.

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I2C Target Control Register

Table 22-68 TCTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h
10	TWUEN	R/W	1h	Target Wakeup Enable 0h = When 0, the Target is not allowed to clock stretch on START detection 1h = When 1, the Target is allowed to clock stretch on START detection and wait for faster clock to be abvailable. This allows clean wake up support for I2C in low power mode use cases
9	EN_DEFDEVADR	R/W	0h	Enable Deault device address 0h = When this bit is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2. 1h = When this bit is 1, default device address of 7’h110_0001 is always matched by the Target address match logic.
8	EN_ALRESPADR	R/W	0h	Enable Alert Response Address 0h = When this bit is 0, the alert response address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2 1h = When this bit is 1, alert response address of 7’h000_1100 is always matched by the Target address match logic.
7	EN_DEFHOSTADR	R/W	0h	Enable Default Host Address 0h = When this bit is 0, the default host address is not matched NOTE: it may still be matched if programmed inside SOAR/SOAR2 1h = When this bit is 1, default host address of 7’h000_1000 is always matched by the Target address match logic.
6	RXFULL_ON_RREQ	R/W	0h	Rx full interrupt generated on RREQ condition as indicated in SSR 0h = When 0, RIS:TRXFULL will be set when only the Target RX FIFO is full. This allows the TRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current Rx byte. 1h = When 1, RIS:TRXFULL will be set when the Target State Machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the I2C transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte.
5	TXWAIT_STALE_TXFIFO	R/W	0h	Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0h = When 0, the TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty. 1h = When 1, the TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the Target State Machine leaves the TXMODE as defined in the SSR register. This can occur is a Stop or timeout occur when there are bytes left in the TX FIFO.
4	TXTRIG_TXMODE	R/W	0h	Tx Trigger when Target FSM is in Tx Mode 0h = No special behavior 1h = When 1, RIS:TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the Target State Machine is in the TXMODE as defined in the SSR register. When cleared RIS:TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time.
3	TXEMPTY_ON_TREQ	R/W	0h	Tx Empty Interrupt on TREQ 0h = When 0, RIS:TTXEMPTY will be set when only the Target TX FIFO is empty. This allows the TTXEMPTY interrupt to be used to indicate that the I2C bus is being clock stretched and that Target TX data is required. 1h = When 1, RIS:TTXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty AND the I2C transaction is clock stretched waiting for the FIFO to receive data.
2	TCLKSTRETCH	R/W	1h	Target Clock Stretch Enable 0h = Target clock stretching is disabled 1h = Target clock stretching is enabled
1	GENCALL	R/W	0h	General call response enable Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0h = Do not respond to a general call 1h = Respond to a general call
0	ACTIVE	R/W	0h	Device Active. Setting this bit enables the Target functionality. 0h = Disables the I2C Target operation. 1h = Enables the I2C Target operation.

22.3.47 TSR Register (Offset = 125Ch) [Reset = 00000000h]

TSR is shown in Table 22-69.

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This register functions as a control register when written, and a status register when read.

Table 22-69 TSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	0h
18-9	ADDRMATCH	R	0h	Indicates the address for which Target address match happened 0h = Minimum Value 3FFh = Maximum Value
8	STALE_TXFIFO	R	0h	Stale Tx FIFO 0h = Tx FIFO is not stale 1h = The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous I2C transaction.
7	TXMODE	R	0h	Target FSM is in TX MODE 0h = The Target State Machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 1h = The Target State Machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
6	BUSBSY	R	0h	I2C bus is busy 0h = The I2C Bus is not busy 1h = The I2C Bus is busy. This is cleared on a timeout.
5	QCMDRW	R	0h	Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0h = Quick command was a write 1h = Quick command was a read
4	QCMDST	R	0h	Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0h = The last transaction was a normal transaction or a transaction has not occurred. 1h = The last transaction was a Quick Command transaction.
3	OAR2SEL	R	0h	OAR2 Address Matched This bit gets reevaluated after every address comparison. 0h = Either the OAR2 address is not matched or the match is in legacy mode. 1h = OAR2 address matched and ACKed by the Target.
2	RXMODE	R	0h	Target FSM is in Rx MODE 0h = The Target State Machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 1h = The Target State Machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
1	TREQ	R	0h	Transmit Request 0h = No outstanding transmit request. 1h = The I2C controller has been addressed as a Target transmitter and is using clock stretching to delay the Controller until data has been written to the TTXDATA FIFO (Target TX FIFO is empty).
0	RREQ	R	0h	Receive Request 0h = No outstanding receive data. 1h = The I2C controller has outstanding receive data from the I2C Controller and is using clock stretching to delay the Controller until the data has been read from the TRXDATA FIFO (Target RX FIFO is full).

22.3.48 TRXDATA Register (Offset = 1260h) [Reset = 00000000h]

TRXDATA is shown in Table 22-70.

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I2C Target RX FIFO Read Data Byte
This field contains the current byte being read in the RX FIFO stack.
If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Table 22-70 TRXDATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	VALUE	R	0h	Received Data. This field contains the last received data. 0h = Smallest value FFh = Highest possible value

22.3.49 TTXDATA Register (Offset = 1264h) [Reset = 00000000h]

TTXDATA is shown in Table 22-71.

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I2C Target Transmit Data Register.
This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).

Table 22-71 TTXDATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	VALUE	R/W	0h	Transmit Data This byte contains the data to be transferred during the next transaction. 0h = Smallest value FFh = Highest possible value

22.3.50 TACKCTL Register (Offset = 1268h) [Reset = 00000000h]

TACKCTL is shown in Table 22-72.

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This register enables the I2C Target to Not Acknowledge (NACK) for invalid data or command or Acknowledge (ACK) for valid data or command. The I2C clock is pulled low after the last data bit until this register is written.

Table 22-72 TACKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h
4	ACKOEN_ON_PECDONE	R/W	0h	When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0h = No special behavior 1h = When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte.
3	ACKOEN_ON_PECNEXT	R/W	0h	When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0h = No special behavior 1h = When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL.
2	ACKOEN_ON_START	R/W	0h	When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0h = No special behavior 1h = When set this bit will automatically turn on the Target ACKOEN field following a Start Condition.
1	ACKOVAL	R/W	0h	I2C Target ACK Override Value Note: for General Call this bit will be ignored if set to NACK and Target continues to receive data. 0h = An ACK is sent indicating valid data or command. 1h = A NACK is sent indicating invalid data or command.
0	ACKOEN	R/W	0h	I2C Target ACK Override Enable 0h = A response in not provided. 1h = An ACK or NACK is sent according to the value written to the ACKOVAL bit.

22.3.51 TFIFOCTL Register (Offset = 126Ch) [Reset = 00000000h]

TFIFOCTL is shown in Table 22-73.

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I2C Target FIFO Control

Table 22-73 TFIFOCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	RXFLUSH	R/W	0h	RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO
14-11	RESERVED	R	0h
10-8	RXTRIG	R/W	0h	RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 4h = Trigger when RX FIFO contains >= 5 byte 5h = Trigger when RX FIFO contains >= 6 byte 6h = Trigger when RX FIFO contains >= 7 byte 7h = Trigger when RX FIFO contains >= 8 byte
7	TXFLUSH	R/W	0h	TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO
6-3	RESERVED	R	0h
2-0	TXTRIG	R/W	0h	TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 4h = Trigger when TX FIFO contains ≤ 4 byte 5h = Trigger when TX FIFO contains ≤ 5 byte 6h = Trigger when TX FIFO contains ≤ 6 byte 7h = Trigger when TX FIFO contains ≤ 7 byte

22.3.52 TFIFOSR Register (Offset = 1270h) [Reset = 00000800h]

TFIFOSR is shown in Table 22-74.

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I2C Target FIFO Status Register
Note: this Register should only be read when BUSY is 0

Table 22-74 TFIFOSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15	TXFLUSH	R	0h	TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active
14-12	RESERVED	R	0h
11-8	TXFIFOCNT	R	8h	Number of Bytes which could be put into the TX FIFO 0h = Smallest value 8h = Highest possible value
7	RXFLUSH	R	0h	RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0h = FIFOFlush not active 1h = FIFO Flush active
6-4	RESERVED	R	0h
3-0	RXFIFOCNT	R	0h	Number of Bytes which could be read from the RX FIFO 0h = Smallest value 8h = Highest possible value

22.3.53 _PECCTL Register (Offset = 1274h) [Reset = 00000000h]

_PECCTL is shown in Table 22-75.

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I2C Target PEC Control Register

Table 22-75 _PECCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h
12	PECEN	R/W	0h	PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0h = PEC transmission and check is disabled 1h = PEC transmission and check is enabled
11-9	RESERVED	R	0h
8-0	PECCNT	R/W	0h	When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Target use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0h = Minimum Value 1FFh = Maximum Value

22.3.54 _PECSR Register (Offset = 1278h) [Reset = 00000000h]

_PECSR is shown in Table 22-76.

Return to the Summary Table.

Target PEC Status Register

Table 22-76 _PECSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h
17	PECSTS_ERROR	R	0h	This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0h = Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 1h = Indicates PEC check error occurred in the transaction that occurred before the last Stop
16	PECSTS_CHECK	R	0h	This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0h = Indicates PEC was not checked in the transaction that occurred before the last Stop 1h = Indicates PEC was checked in the transaction that occurred before the last Stop
15-9	RESERVED	R	0h
8-0	PECBYTECNT	R	0h	This is the current PEC Byte Count of the Target State Machine. 0h = Minimum Value 1FFh = Maximum Value

22.3 I2C Registers

22.3.1 PWREN Register (Offset = 800h) [Reset = 00000000h]

22.3.2 RSTCTL Register (Offset = 804h) [Reset = 00000000h]

22.3.3 CLKCFG Register (Offset = 808h) [Reset = 00000000h]

22.3.4 STAT Register (Offset = 814h) [Reset = 00000000h]

22.3.5 CLKDIV Register (Offset = 1000h) [Reset = 00000000h]

22.3.6 CLKSEL Register (Offset = 1004h) [Reset = 00000000h]

22.3.7 PDBGCTL Register (Offset = 1018h) [Reset = 00000000h]

22.3.8 IIDX Register (Offset = 1020h) [Reset = 00000000h] (CPU_INT)

22.3.9 IMASK Register (Offset = 1028h) [Reset = 00000000h] (CPU_INT)

22.3.10 RIS Register (Offset = 1030h) [Reset = 00000000h] (CPU_INT)

22.3.11 MIS Register (Offset = 1038h) [Reset = 00000000h] (CPU_INT)

22.3.12 ISET Register (Offset = 1040h) [Reset = 00000000h] (CPU_INT)

22.3.13 ICLR Register (Offset = 1048h) [Reset = 00000000h] (CPU_INT)

22.3.14 IIDX Register (Offset = 1050h) [Reset = 00000000h] (DMA_TRIG1)

22.3.15 IMASK Register (Offset = 1058h) [Reset = 00000000h] (DMA_TRIG1)

22.3.16 RIS Register (Offset = 1060h) [Reset = 00000000h] (DMA_TRIG1)

22.3.17 MIS Register (Offset = 1068h) [Reset = 00000000h] (DMA_TRIG1)

22.3.18 ISET Register (Offset = 1070h) [Reset = 00000000h] (DMA_TRIG1)

22.3.19 ICLR Register (Offset = 1078h) [Reset = 00000000h] (DMA_TRIG1)

22.3.20 IIDX Register (Offset = 1080h) [Reset = 00000000h] (DMA_TRIG0)

22.3.21 IMASK Register (Offset = 1088h) [Reset = 00000000h] (DMA_TRIG0)

22.3.22 RIS Register (Offset = 1090h) [Reset = 00000000h] (DMA_TRIG0)

22.3.23 MIS Register (Offset = 1098h) [Reset = 00000000h] (DMA_TRIG0)

22.3.24 ISET Register (Offset = 10A0h) [Reset = 00000000h] (DMA_TRIG0)

22.3.25 ICLR Register (Offset = 10A8h) [Reset = 00000000h] (DMA_TRIG0)

22.3.26 EVT_MODE Register (Offset = 10E0h) [Reset = 00000000h]

22.3.27 INTCTL Register (Offset = 10E4h) [Reset = 00000000h]

22.3.28 DESC Register (Offset = 10FCh) [Reset = 00000000h]

22.3.29 GFCTL Register (Offset = 1200h) [Reset = 00000000h]

22.3.30 TIMEOUT_CTL Register (Offset = 1204h) [Reset = 00020002h]

22.3.31 TIMEOUT_CNT Register (Offset = 1208h) [Reset = 00020002h]

22.3.32 CSA Register (Offset = 1210h) [Reset = 00000000h]

22.3.33 CCTR Register (Offset = 1214h) [Reset = 00000000h]

22.3.34 CSR Register (Offset = 1218h) [Reset = 00000000h]

22.3.35 CRXDATA Register (Offset = 121Ch) [Reset = 00000000h]

22.3.36 CTXDATA Register (Offset = 1220h) [Reset = 00000000h]

22.3.37 CTPR Register (Offset = 1224h) [Reset = 00000001h]

22.3.38 CCR Register (Offset = 1228h) [Reset = 00000000h]

22.3.39 CBMON Register (Offset = 1234h) [Reset = 00000003h]

22.3.40 CFIFOCTL Register (Offset = 1238h) [Reset = 00000000h]

22.3.41 CFIFOSR Register (Offset = 123Ch) [Reset = 00000800h]

22.3.42 _I2CPECCTL Register (Offset = 1240h) [Reset = 00000000h]

22.3.43 _PECSR Register (Offset = 1244h) [Reset = 00000000h]

22.3.44 TOAR Register (Offset = 1250h) [Reset = 00004000h]

22.3.45 TOAR2 Register (Offset = 1254h) [Reset = 00000000h]

22.3.46 TCTR Register (Offset = 1258h) [Reset = 00000404h]

22.3.47 TSR Register (Offset = 125Ch) [Reset = 00000000h]

22.3.48 TRXDATA Register (Offset = 1260h) [Reset = 00000000h]

22.3.49 TTXDATA Register (Offset = 1264h) [Reset = 00000000h]

22.3.50 TACKCTL Register (Offset = 1268h) [Reset = 00000000h]

22.3.51 TFIFOCTL Register (Offset = 126Ch) [Reset = 00000000h]

22.3.52 TFIFOSR Register (Offset = 1270h) [Reset = 00000800h]

22.3.53 _PECCTL Register (Offset = 1274h) [Reset = 00000000h]

22.3.54 _PECSR Register (Offset = 1278h) [Reset = 00000000h]