SLAU847E October   2022  â€“ May 2025 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 RTCCLK (RTC Clock)
        11. 2.3.2.11 External Clock Output (CLK_OUT)
        12. 2.3.2.12 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.5.7 Optimizing for Lowest Wakeup Latency
      8. 2.5.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Layout Types
    7. 2.7 SYSCTL_TYPEA Registers
    8. 2.8 SYSCTL_TYPEB Registers
    9. 2.9 SYSCTL_TYPEC Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 DMA
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AESADV
    1. 10.1 AESADV Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24Timers (TIMx)
    1. 24.1 TIMx Overview
      1. 24.1.1 TIMG Overview
        1. 24.1.1.1 TIMG Features
        2. 24.1.1.2 Functional Block Diagram
      2. 24.1.2 TIMA Overview
        1. 24.1.2.1 TIMA Features
        2. 24.1.2.2 Functional Block Diagram
      3. 24.1.3 TIMx Instance Configuration
    2. 24.2 TIMx Operation
      1. 24.2.1  Timer Counter
        1. 24.2.1.1 Clock Source Select and Prescaler
          1. 24.2.1.1.1 Internal Clock and Prescaler
          2. 24.2.1.1.2 External Signal Trigger
        2. 24.2.1.2 Repeat Counter (TIMA only)
      2. 24.2.2  Counting Mode Control
        1. 24.2.2.1 One-shot and Periodic Modes
        2. 24.2.2.2 Down Counting Mode
        3. 24.2.2.3 Up/Down Counting Mode
        4. 24.2.2.4 Up Counting Mode
        5. 24.2.2.5 Phase Load (TIMA only)
      3. 24.2.3  Capture/Compare Module
        1. 24.2.3.1 Capture Mode
          1. 24.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 24.2.3.1.1.1 CCP Input Edge Synchronization
            2. 24.2.3.1.1.2 CCP Input Pulse Conditions
            3. 24.2.3.1.1.3 Counter Control Operation
            4. 24.2.3.1.1.4 CCP Input Filtering
            5. 24.2.3.1.1.5 Input Selection
          2. 24.2.3.1.2 Use Cases
            1. 24.2.3.1.2.1 Edge Time Capture
            2. 24.2.3.1.2.2 Period Capture
            3. 24.2.3.1.2.3 Pulse Width Capture
            4. 24.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 24.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 24.2.3.1.3.1 QEI With 2-Signal
            2. 24.2.3.1.3.2 QEI With Index Input
            3. 24.2.3.1.3.3 QEI Error Detection
          4. 24.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 24.2.3.2 Compare Mode
          1. 24.2.3.2.1 Edge Count
      4. 24.2.4  Shadow Load and Shadow Compare
        1. 24.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 24.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 24.2.5  Output Generator
        1. 24.2.5.1 Configuration
        2. 24.2.5.2 Use Cases
          1. 24.2.5.2.1 Edge-Aligned PWM
          2. 24.2.5.2.2 Center-Aligned PWM
          3. 24.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 24.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 24.2.5.3 Forced Output
      6. 24.2.6  Fault Handler (TIMA only)
        1. 24.2.6.1 Fault Input Conditioning
        2. 24.2.6.2 Fault Input Sources
        3. 24.2.6.3 Counter Behavior With Fault Conditions
        4. 24.2.6.4 Output Behavior With Fault Conditions
      7. 24.2.7  Synchronization With Cross Trigger
        1. 24.2.7.1 Main Timer Cross Trigger Configuration
        2. 24.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 24.2.8  Low Power Operation
      9. 24.2.9  Interrupt and Event Support
        1. 24.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 24.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 24.2.10 Debug Handler (TIMA Only)
    3. 24.3 TIMx Registers
  27. 25Low Frequency Subsystem (LFSS)
    1. 25.1  Overview
    2. 25.2  Clock System
    3. 25.3  LFSS Reset Using VBAT
    4. 25.4  Power Domains and Supply Detection
      1. 25.4.1 Startup When VBAT Powers on First
      2. 25.4.2 Startup when VDD powers on first
      3. 25.4.3 Behavior When VDD is Lost
      4. 25.4.4 Behavior when VBAT is lost
      5. 25.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 25.4.6 Supercapacitor Charging Circuit
    5. 25.5  Real Time Counter (RTC_x)
    6. 25.6  Independent Watchdog Timer (IWDT)
    7. 25.7  Tamper Input and Output
      1. 25.7.1 IOMUX Mode
      2. 25.7.2 Tamper Mode
        1. 25.7.2.1 Tamper Event Detection
        2. 25.7.2.2 Timestamp Event Output
        3. 25.7.2.3 Heartbeat Generator
        4. 25.7.2.4 RTC Clock Output
    8. 25.8  Scratchpad Memory
    9. 25.9  Lock Function of RTC, TIO, and IWDT
    10. 25.10 LFSS Registers
  28. 26Low Frequency Subsystem (LFSS_B)
    1. 26.1 Overview
    2. 26.2 Clock System
    3. 26.3 LFSS Reset
    4. 26.4 Real Time Counter (RTC_x)
    5. 26.5 Independent Watchdog Timer (IWDT)
    6. 26.6 Lock Function of RTC and IWDT
    7. 26.7 LFSS Registers
  29. 27RTC
    1. 27.1 Overview
      1. 27.1.1 RTC Instances
    2. 27.2 Basic Operation
    3. 27.3 Configuration
      1. 27.3.1  Clocking
      2. 27.3.2  Reading and Writing to RTC Peripheral Registers
      3. 27.3.3  Binary vs. BCD
      4. 27.3.4  Leap Year Handling
      5. 27.3.5  Calendar Alarm Configuration
      6. 27.3.6  Interval Alarm Configuration
      7. 27.3.7  Periodic Alarm Configuration
      8. 27.3.8  Calibration
        1. 27.3.8.1 Crystal Offset Error
          1. 27.3.8.1.1 Offset Error Correction Mechanism
        2. 27.3.8.2 Crystal Temperature Error
          1. 27.3.8.2.1 Temperature Drift Correction Mechanism
      9. 27.3.9  RTC Prescaler Extension
      10. 27.3.10 RTC Timestamp Capture
      11. 27.3.11 RTC Events
        1. 27.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 27.4 RTC Registers
  30. 28IWDT
    1. 28.1 734
    2. 28.2 IWDT Clock Configuration
    3. 28.3 IWDT Period Selection
    4. 28.4 Debug Behavior of the IWDT
    5. 28.5 IWDT Registers
  31. 29WWDT
    1. 29.1 WWDT Overview
      1. 29.1.1 Watchdog Mode
      2. 29.1.2 Interval Timer Mode
    2. 29.2 WWDT Operation
      1. 29.2.1 Mode Selection
      2. 29.2.2 Clock Configuration
      3. 29.2.3 Low-Power Mode Behavior
      4. 29.2.4 Debug Behavior
      5. 29.2.5 WWDT Events
        1. 29.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 29.3 WWDT Registers
  32. 30Debug
    1. 30.1 DEBUGSS Overview
      1. 30.1.1 Debug Interconnect
      2. 30.1.2 Physical Interface
      3. 30.1.3 Debug Access Ports
    2. 30.2 DEBUGSS Operation
      1. 30.2.1 Debug Features
        1. 30.2.1.1 Processor Debug
          1. 30.2.1.1.1 Breakpoint Unit (BPU)
          2. 30.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 30.2.1.2 Peripheral Debug
        3. 30.2.1.3 EnergyTrace Technology
      2. 30.2.2 Behavior in Low Power Modes
      3. 30.2.3 Restricting Debug Access
      4. 30.2.4 Mailbox (DSSM)
        1. 30.2.4.1 DSSM Events
          1. 30.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 30.2.4.2 Reference
    3. 30.3 DEBUGSS Registers
  33. 31Revision History

27.4 RTC Registers

Table 27-5 lists the memory-mapped registers for the RTC registers. All register offset addresses not listed in Table 27-5 should be considered as reserved locations and the register contents should not be modified.

Table 27-5 RTC Registers
OffsetAcronymRegister NameGroupSection
444hFPUB_0Publisher Port 0Go
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
808hCLKCFGPeripheral Clock Configuration RegisterGo
814hSTATStatus RegisterGo
1004hCLKSELClock Select for Ultra Low Power peripheralsGo
1020hIIDXInterrupt Index RegisterCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt Index RegisterGEN_EVENTGo
1054hIMASKInterrupt maskGEN_EVENTGo
1058hRISRaw interrupt statusGEN_EVENTGo
105ChMISMasked interrupt statusGEN_EVENTGo
1060hISETInterrupt setGEN_EVENTGo
1064hICLRInterrupt clearGEN_EVENTGo
10E0hEVT_MODEEvent ModeGo
10FChDESCRTC Descriptor RegisterGo
1100hCLKCTLRTC Clock Control RegisterGo
1104hDBGCTLRTC Module Debug Control RegisterGo
1108hCTLRTC Control RegisterGo
110ChSTARTC Status RegisterGo
1110hCALRTC Clock Offset Calibration RegisterGo
1114hTCMPRTC Temperature Compensation RegisterGo
1118hSECRTC Seconds Register - Calendar Mode With Binary / BCD FormatGo
111ChMINRTC Minutes Register - Calendar Mode With Binary / BCD FormatGo
1120hHOURRTC Hours Register - Calendar Mode With Binary / BCD FormatGo
1124hDAYRTC Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1128hMONRTC Month Register - Calendar Mode With Binary / BCD FormatGo
112ChYEARRTC Year Register - Calendar Mode With Binary / BCD FormatGo
1130hA1MINRTC Minute Alarm Register - Calendar Mode With Binary / BCD FormatGo
1134hA1HOURRTC Hours Alarm Register - Calendar Mode With Binary / BCD FormatGo
1138hA1DAYRTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
113ChA2MINRTC Minute Alarm Register - Calendar Mode With Binary / BCD FormatGo
1140hA2HOURRTC Hours Alarm Register - Calendar Mode With Binary / BCD FormatGo
1144hA2DAYRTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1148hPSCTLRTC Prescale Timer 0/1 Control RegisterGo
114ChEXTPSCTLRTC Prescale Timer 2 Control RegisterGo
1150hTSSECTime Stamp Seconds Register - Calendar Mode With Binary / BCD FormatGo
1154hTSMINTime Stamp Minutes Register - Calendar Mode With Binary / BCD FormatGo
1158hTSHOURTime Stamp Hours Register - Calendar Mode With Binary / BCD FormatGo
115ChTSDAYTime Stamp Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1160hTSMONTime Stamp Month Register - Calendar Mode With Binary / BCD FormatGo
1164hTSYEARTime Stamp Years Register - Calendar Mode With Binary / BCD FormatGo
1168hTSSTATTime Stamp Status RegisterGo
116ChTSCTLTime Stamp Control RegisterGo
1170hTSCLRTime Stamp Clear RegisterGo
1174hLFSSRSTLow frequency subsystem reset requestGo
1178hRTCLOCKReal time clock lock registerGo

Complex bit access types are encoded to fit into small table cells. Table 27-6 shows the codes that are used for access types in this section.

Table 27-6 RTC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

27.4.1 FPUB_0 (Offset = 444h) [Reset = 00000000h]

FPUB_0 is shown in Figure 27-5 and described in Table 27-7.

Return to the Summary Table.

Publisher port

Figure 27-5 FPUB_0
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCHANID
R-0hR/W-0h
Table 27-7 FPUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

27.4.2 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 27-6 and described in Table 27-8.

Return to the Summary Table.

Register to control the power state

Figure 27-6 PWREN
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENABLE
R-0hR/WK-0h
Table 27-8 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR0h
0ENABLER/WK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

27.4.3 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 27-7 and described in Table 27-9.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 27-7 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
R-0hWK-0hWK-0h
Table 27-9 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDR0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

27.4.4 CLKCFG (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 27-8 and described in Table 27-10.

Return to the Summary Table.

Peripheral Clock Configuration Register

Figure 27-8 CLKCFG
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDBLOCKASYNC
R-0hR/WK-0h
76543210
RESERVED
R-0h
Table 27-10 CLKCFG Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hKEY to Allow State Change -- 0xA9
A9h (W) = key value to allow change field of GPRCM
23-9RESERVEDR0h
8BLOCKASYNCR/WK0hAsync Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz

KEY must be set to A9h to write to this bit.


0h = Not block async clock request
1h = Block async clock request
7-0RESERVEDR0h

27.4.5 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 27-9 and described in Table 27-11.

Return to the Summary Table.

peripheral enable and reset status

Figure 27-9 STAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 27-11 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

27.4.6 CLKSEL (Offset = 1004h) [Reset = 00000000h]

CLKSEL is shown in Figure 27-10 and described in Table 27-12.

Return to the Summary Table.

Clock source selection for ULP peripherals

Figure 27-10 CLKSEL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLFCLK_SELRESERVED
R-0hR-0hR-0h
Table 27-12 CLKSEL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1LFCLK_SELR0hSelects LFCLK as clock source if enabled
0h = LFCLK is disabled as clock source
1h = LFCLK is enabled as clock source
0RESERVEDR0h

27.4.7 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 27-11 and described in Table 27-13.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 27-11 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 27-13 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = RTC-Ready interrupt; Interrupt flag: RTCRDY
2h = Time-Event interrupt; Interrupt flag: RTCTEV
3h = Alarm-1 interrupt; Interrupt flag: RTCA1
4h = Alarm-2 interrupt; Interrupt flag: RTCA2
5h = Prescaler-0 interrupt; Interrupt flag: RT0PS
6h = Prescaler-1 interrupt; Interrupt flag: RT1PS
07h = RTC prescale timer 2
08h = Time stamp event
09h = Tamper I/O 0 event
0Ah = Tamper I/O 1 event
0Bh = Tamper I/O 2 event
0Ch = Tamper I/O 3 event
0Dh = Tamper I/O 4 event
0Eh = Tamper I/O 5 event
0Fh = Tamper I/O 6 event
10h = Tamper I/O 7 event
11h = Tamper I/O 8 event
12h = Tamper I/O 9 event
13h = Tamper I/O 10 event
14h = Tamper I/O 11 event
15h = Tamper I/O 12 event
16h = Tamper I/O 13 event
17h = Tamper I/O 14 event
18h = Tamper I/O 15 event

27.4.8 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 27-12 and described in Table 27-14.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 27-12 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 27-14 IMASK Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R/W0hTamper I/O 15 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
22TIO14R/W0hTamper I/O 14 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
21TIO13R/W0hTamper I/O 13 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
20TIO12R/W0hTamper I/O 12 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
19TIO11R/W0hTamper I/O 11 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
18TIO10R/W0hTamper I/O 10 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
17TIO9R/W0hTamper I/O 9 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
16TIO8R/W0hTamper I/O 8 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
15TIO7R/W0hTamper I/O 7 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14TIO6R/W0hTamper I/O 6 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13TIO5R/W0hTamper I/O 5 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12TIO4R/W0hTamper I/O 4 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11TIO3R/W0hTamper I/O 3 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10TIO2R/W0hTamper I/O 2 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9TIO1R/W0hTamper I/O 1 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8TIO0R/W0hTamper I/O 0 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7TSEVTR/W0hTime stamp event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6RT2PSR/W0hRTC prescale timer 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5RT1PSR/W0hEnable Prescaler-1 interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4RT0PSR/W0hEnable Prescaler-0 interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3RTCA2R/W0hEnable Alarm-2 interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RTCA1R/W0hEnable Alarm-1 interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1RTCTEVR/W0hEnable Time-Event interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RTCRDYR/W0hEnable RTC-Ready interrupt
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

27.4.9 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 27-13 and described in Table 27-15.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 27-13 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-15 RIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur
1h = Interrupt occurred
5RT1PSR0hRaw Prescaler-1 interrupt status


0h = Interrupt did not occur
1h = Interrupt occurred
4RT0PSR0hRaw Prescaler-0 interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
3RTCA2R0hRaw Alarm-2 interrupts status
0h = Interrupt did not occur
1h = Interrupt occurred
2RTCA1R0hRaw Alarm-1 interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
1RTCTEVR0hRaw Time-Event interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
0RTCRDYR0hRaw RTC-Ready interrupts status
0h = Interrupt did not occur
1h = Interrupt occurred

27.4.10 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 27-14 and described in Table 27-16.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 27-14 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-16 MIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5RT1PSR0hMasked Prescaler-1 interrupt status

0h = Interrupt did not occur
1h = Interrupt occurred
4RT0PSR0hMasked Prescaler-0 interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
3RTCA2R0hMasked Alarm-2 interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
2RTCA1R0hMasked Alarm-1 interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
1RTCTEVR0hMasked Time-Event interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred
0RTCRDYR0hMasked RTC-Ready interrupt status
0h = Interrupt did not occur
1h = Interrupt occurred

27.4.11 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 27-15 and described in Table 27-17.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 27-15 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-17 ISET Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Set interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Set interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Set interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Set interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Set interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Set interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Set interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Set interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Set interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Set interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Set interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Set interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Set interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Set interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Set interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Set interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Set interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Set interrupt
5RT1PSW0hSet Prescaler-1 interrupt
0h = Writing 0 has no effect
1h = Set Interrupt
4RT0PSW0hSet Prescaler-0 interrupt
0h = Writing 0 has no effect
1h = Set Interrupt
3RTCA2W0hSet Alarm-2 interrupt
0h = Writing 0 has no effect
1h = Set Interrupt
2RTCA1W0hSet Alarm-1 interrupt
0h = Writing 0 has no effect
1h = Set Interrupt
1RTCTEVW0hSet Time-Event interrupt
0h = Writing 0 has no effect
1h = Set Interrupt
0RTCRDYW0hSet RTC-Ready interrupt
0h = Writing 0 has no effect
1h = Set Interrupt

27.4.12 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 27-16 and described in Table 27-18.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 27-16 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-18 ICLR Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Clear interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Clear interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Clear interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Clear interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Clear interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Clear interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Clear interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Clear interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Clear interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Clear interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Clear interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Clear interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Clear interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Clear interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Clear interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Clear interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Clear interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Clear interrupt
5RT1PSW0hClear Prescaler-1 interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt
4RT0PSW0hClear Prescaler-0 interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt
3RTCA2W0hClear Alarm-2 interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt
2RTCA1W0hClear Alarm-1 interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt
1RTCTEVW0hClear Time-Event interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt
0RTCRDYW0hClear RTC-Ready interrupt
0h = Writing 0 has no effect
1h = Clear Interrupt

27.4.13 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 27-17 and described in Table 27-19.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 27-17 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 27-19 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = RTC ready
02h = RTC time event
03h = RTC alarm 1
04h = RTC alarm 2
05h = RTC prescale timer 0
06h = RTC prescale timer 1
07h = RTC prescale timer 2
08h = Time stamp event
09h = Tamper I/O 0 event
0Ah = Tamper I/O 1 event
0Bh = Tamper I/O 2 event
0Ch = Tamper I/O 3 event
0Dh = Tamper I/O 4 event
0Eh = Tamper I/O 5 event
0Fh = Tamper I/O 6 event
10h = Tamper I/O 7 event
11h = Tamper I/O 8 event
12h = Tamper I/O 9 event
13h = Tamper I/O 10 event
14h = Tamper I/O 11 event
15h = Tamper I/O 12 event
16h = Tamper I/O 13 event
17h = Tamper I/O 14 event
18h = Tamper I/O 15 event

27.4.14 IMASK (Offset = 1054h) [Reset = 00000000h]

IMASK is shown in Figure 27-18 and described in Table 27-20.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 27-18 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 27-20 IMASK Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R/W0hTamper I/O 15 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
22TIO14R/W0hTamper I/O 14 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
21TIO13R/W0hTamper I/O 13 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
20TIO12R/W0hTamper I/O 12 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
19TIO11R/W0hTamper I/O 11 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
18TIO10R/W0hTamper I/O 10 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
17TIO9R/W0hTamper I/O 9 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
16TIO8R/W0hTamper I/O 8 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
15TIO7R/W0hTamper I/O 7 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14TIO6R/W0hTamper I/O 6 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13TIO5R/W0hTamper I/O 5 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12TIO4R/W0hTamper I/O 4 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11TIO3R/W0hTamper I/O 3 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10TIO2R/W0hTamper I/O 2 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9TIO1R/W0hTamper I/O 1 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8TIO0R/W0hTamper I/O 0 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7TSEVTR/W0hTime stamp event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6RT2PSR/W0hRTC prescale timer 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5RT1PSR/W0hRTC prescale timer 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4RT0PSR/W0hRTC prescale timer 0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3RTCA2R/W0hRTC alarm 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RTCA1R/W0hRTC alarm 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1RTCTEVR/W0hRTC time event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RTCRDYR/W0hRTC ready
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

27.4.15 RIS (Offset = 1058h) [Reset = 00000000h]

RIS is shown in Figure 27-19 and described in Table 27-21.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 27-19 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-21 RIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur
1h = Interrupt occurred

27.4.16 MIS (Offset = 105Ch) [Reset = 00000000h]

MIS is shown in Figure 27-20 and described in Table 27-22.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 27-20 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-22 MIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

27.4.17 ISET (Offset = 1060h) [Reset = 00000000h]

ISET is shown in Figure 27-21 and described in Table 27-23.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 27-21 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-23 ISET Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Set interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Set interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Set interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Set interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Set interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Set interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Set interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Set interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Set interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Set interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Set interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Set interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Set interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Set interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Set interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Set interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Set interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Set interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Set interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Set interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Set interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Set interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Set interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Set interrupt

27.4.18 ICLR (Offset = 1064h) [Reset = 00000000h]

ICLR is shown in Figure 27-22 and described in Table 27-24.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 27-22 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-24 ICLR Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Clear interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Clear interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Clear interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Clear interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Clear interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Clear interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Clear interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Clear interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Clear interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Clear interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Clear interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Clear interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Clear interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Clear interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Clear interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Clear interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Clear interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Clear interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Clear interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Clear interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Clear interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Clear interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Clear interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Clear interrupt

27.4.19 EVT_MODE (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 27-23 and described in Table 27-25.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 27-23 EVT_MODE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEVT1_CFGEVT0_CFG
R-0hR-0hR-0h
Table 27-25 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-2EVT1_CFGR0hEvent line mode 1 select
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. The software ISR clears the associated RIS flag.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0EVT0_CFGR0hEvent line mode 0 select
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. The software ISR clears the associated RIS flag.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

27.4.20 DESC (Offset = 10FCh) [Reset = 09118010h]

DESC is shown in Figure 27-24 and described in Table 27-26.

Return to the Summary Table.

RTC Descriptor Register

Figure 27-24 DESC
31302928272625242322212019181716
MODULEID
R-911h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-8hR-0hR-1hR-0h
Table 27-26 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR911h Module identifier. This ID is unique for each module. 0x0911 = Module ID of the RTC Module
0000h = Minimum value
FFFFh = Maximum value
15-12FEATUREVERR8h Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences.
0h = Minimum value
Fh = Maximum value
11-8INSTNUMR0h Instantiated version. Describes which instance of the module accessed.
0h = This is the default, if there is only one instance - like for SSIM
7-4MAJREVR1h Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)
0h = Minimum value
Fh = Maximum value
3-0MINREVR0hMinor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)
0h = Minimum value
Fh = Maximum value

27.4.21 CLKCTL (Offset = 1100h) [Reset = 00000000h]

CLKCTL is shown in Figure 27-25 and described in Table 27-27.

Return to the Summary Table.

RTC Clock Control Register

Figure 27-25 CLKCTL
3130292827262524
MODCLKENRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 27-27 CLKCTL Field Descriptions
BitFieldTypeResetDescription
31MODCLKENR/W0hThis bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module.
0h = 32kHz clock is not supplied to the RTC.
1h = 32kHz clock is supplied to the RTC.
30-0RESERVEDR0h

27.4.22 DBGCTL (Offset = 1104h) [Reset = 00000000h]

DBGCTL is shown in Figure 27-26 and described in Table 27-28.

Return to the Summary Table.

RTC Module Debug Control Register

Figure 27-26 DBGCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDBGINTDBGRUN
R-0hR/W-0hR/W-0h
Table 27-28 DBGCTL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1DBGINTR/W0hDebug Interrupt Enable.
0h = Interrupts of the module will not be captured anymore if CPU is in debug state. Which means no update to the RTCRIS, RTCMISC and RTCIIDX register.
1h = Interrupts are enabled in debug mode. Interrupt requests are signaled to the interrupt controller. If the flags are required by software (polling mode) the DGBINT bit need to be set to 1.
0DBGRUNR/W0hDebug Run.
0h = Counter is halted if CPU is in debug state.
1h = Continue to operate normally ignoring the debug state of the CPU.

27.4.23 CTL (Offset = 1108h) [Reset = 00000000h]

CTL is shown in Figure 27-27 and described in Table 27-29.

Return to the Summary Table.

RTC Control Register

Figure 27-27 CTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RTCBCDRESERVEDRTCTEVTX
R/W-0hR-0hR/W-0h
Table 27-29 CTL Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7RTCBCDR/W0hReal-time clock BCD select. Selects BCD counting for real-time clock.
0h = Binary code selected
1h = Binary coded decimal (BCD) code selected
6-2RESERVEDR0h
1-0RTCTEVTXR/W0hReal-time clock time event.
0h = Minute changed.
1h = Hour changed.
2h = Every day at midnight (00:00).
3h = Every day at noon (12:00).

27.4.24 STA (Offset = 110Ch) [Reset = 00000000h]

STA is shown in Figure 27-28 and described in Table 27-30.

Return to the Summary Table.

RTC Status Register

Figure 27-28 STA
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRTCTCOKRTCTCRDYRTCRDY
R-0hR-0hR-0hR-0h
Table 27-30 STA Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2RTCTCOKR0hReal-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not.
0h = Write to RTCTCMPx is unsuccessful
1h = Write to RTCTCMPx is successful
1RTCTCRDYR0hReal-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset.
0h = Real-time clock temperature compensation not ready
1h = Real-time clock temperature compensation ready
0RTCRDYR0hReal-time clock ready. This bit indicates when the real-time clock time values are safe for reading.
0h = RTC time values in transition
1h = RTC time values safe for reading

27.4.25 CAL (Offset = 1110h) [Reset = 00000000h]

CAL is shown in Figure 27-29 and described in Table 27-31.

Return to the Summary Table.

RTC Clock Offset Calibration Register

Figure 27-29 CAL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRTCCALFX
R-0hR/W-0h
15141312111098
RTCOCALSRESERVED
R/W-0hR-0h
76543210
RTCOCALX
R/W-0h
Table 27-31 CAL Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17-16RTCCALFXR/W0hReal-time clock calibration frequency. Selects frequency output to RTC_OUT pin for calibration measurement. The corresponding port must be configured for the peripheral module function.
0h = No frequency output to RTC_OUT pin
1h = 512Hz
2h = 256Hz
3h = 1Hz
15RTCOCALSR/W0h Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration.
0h = Down calibration. Frequency adjusted down.
1h = Up calibration. Frequency adjusted up.
14-8RESERVEDR0h
7-0RTCOCALXR/W0hReal-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be ignored by hardware.
0h = Minimum effective calibration value.
FFh = Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be ignored by hardware.

27.4.26 TCMP (Offset = 1114h) [Reset = 00000000h]

TCMP is shown in Figure 27-30 and described in Table 27-32.

Return to the Summary Table.

RTC Temperature Compensation Register

Figure 27-30 TCMP
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RTCTCMPSRESERVED
R/W-0hR-0h
76543210
RTCTCMPX
R/W-0h
Table 27-32 TCMP Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15RTCTCMPSR/W0h Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation.
0h = Down calibration. Frequency adjusted down.
1h = Up calibration. Frequency adjusted up.
14-8RESERVEDR0h
7-0RTCTCMPXR/W0h Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm are ignored by hardware. Reading from RTCTCMP register at any time returns the cumulative value which is the signed addition of RTCOCALx and RTCTCMPX values, and the updated sign bit (RTCTCMPS) of the addition result.
00h = Minimum value
FFh = Maximum value

27.4.27 SEC (Offset = 1118h) [Reset = 0000XXXXh]

SEC is shown in Figure 27-31 and described in Table 27-33.

Return to the Summary Table.

RTC Seconds Register - Calendar Mode With Binary / BCD Format

Figure 27-31 SEC
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSECHIGHBCDSECLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDSECBIN
R-0hR/W-X
Table 27-33 SEC Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12SECHIGHBCDR/WXSeconds BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
5h = Maximum value
11-8SECLOWBCDR/WXSeconds BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7-6RESERVEDR0h
5-0SECBINR/WXSeconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
3Bh = Maximum value

27.4.28 MIN (Offset = 111Ch) [Reset = 0000XXXXh]

MIN is shown in Figure 27-32 and described in Table 27-34.

Return to the Summary Table.

RTC Minutes Register - Calendar Mode With Binary / BCD Format

Figure 27-32 MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMINHIGHBCDMINLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDMINBIN
R-0hR/W-X
Table 27-34 MIN Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12MINHIGHBCDR/WXMinutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
5h = Maximum value
11-8MINLOWBCDR/WXMinutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7-6RESERVEDR0h
5-0MINBINR/WXMinutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
3Bh = Maximum value

27.4.29 HOUR (Offset = 1120h) [Reset = 0000XXXXh]

HOUR is shown in Figure 27-33 and described in Table 27-35.

Return to the Summary Table.

RTC Hours Register - Calendar Mode With Binary / BCD Format

Figure 27-33 HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDHOURHIGHBCDHOURLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDHOURBIN
R-0hR/W-X
Table 27-35 HOUR Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h
13-12HOURHIGHBCDR/WXHours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value.
2h = Maximum value.
11-8HOURLOWBCDR/WXHours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value.
9h = Maximum value.
7-5RESERVEDR0h
4-0HOURBINR/WXHours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value.
17h = Maximum value.

27.4.30 DAY (Offset = 1124h) [Reset = 00XXXX0Xh]

DAY is shown in Figure 27-34 and described in Table 27-36.

Return to the Summary Table.

RTC Day of Week/Month Register - Calendar Mode With Binary / BCD Format

Figure 27-34 DAY
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDOMHIGHBCDDOMLOWBCD
R-0hR/W-XR/W-X
15141312111098
RESERVEDDOMBIN
R-0hR/W-X
76543210
RESERVEDDOW
R-0hR/W-X
Table 27-36 DAY Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-20DOMHIGHBCDR/WX Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
3h = Maximum value
19-16DOMLOWBCDR/WXDay of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
15-13RESERVEDR0h
12-8DOMBINR/WXDay of month Binary (1 to 28, 29, 30, 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
1Fh = Maximum value
7-3RESERVEDR0h
2-0DOWR/WXDay of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Minimum value
6h = Maximum value

27.4.31 MON (Offset = 1128h) [Reset = 0000XX0Xh]

MON is shown in Figure 27-35 and described in Table 27-37.

Return to the Summary Table.

RTC Month Register - Calendar Mode With Binary / BCD Format

Figure 27-35 MON
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMONHIGHBCDMONLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDMONBIN
R-0hR/W-X
Table 27-37 MON Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h
12MONHIGHBCDR/WXMonth BCD – high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
1h = Maximum value
11-8MONLOWBCDR/WXMonth BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7-4RESERVEDR0h
3-0MONBINR/WXMonth Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Minimum value
Ch = Maximum value

27.4.32 YEAR (Offset = 112Ch) [Reset = XXXX0XXXh]

YEAR is shown in Figure 27-36 and described in Table 27-38.

Return to the Summary Table.

RTC Year Register - Calendar Mode With Binary / BCD Format

Figure 27-36 YEAR
3130292827262524
RESERVEDCENTHIGHBCDCENTLOWBCD
R-0hR/W-XR/W-X
2322212019181716
DECADEBCDYEARLOWESTBCD
R/W-XR/W-X
15141312111098
RESERVEDYEARHIGHBIN
R-0hR/W-X
76543210
YEARLOWBIN
R/W-X
Table 27-38 YEAR Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h
30-28CENTHIGHBCDR/WXCentury BCD – high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
4h = Maximum value
27-24CENTLOWBCDR/WXCentury BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
23-20DECADEBCDR/WXDecade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
19-16YEARLOWESTBCDR/WXYear BCD – lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
15-12RESERVEDR0h
11-8YEARHIGHBINR/WXYear Binary – high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Minimum value
Fh = Maximum value
7-0YEARLOWBINR/WXYear Binary – low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
FFh = Maximum value

27.4.33 A1MIN (Offset = 1130h) [Reset = 00000000h]

A1MIN is shown in Figure 27-37 and described in Table 27-39.

Return to the Summary Table.

RTC Minutes Alarm Register - Calendar Mode With Binary / BCD Format

Figure 27-37 A1MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AMINAEBCDAMINHIGHBCDAMINLOWBCD
R/W-0hR/W-0hR/W-0h
76543210
AMINAEBINRESERVEDAMINBIN
R/W-0hR-0hR/W-0h
Table 27-39 A1MIN Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AMINAEBCDR/W0h Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14-12AMINHIGHBCDR/W0h Alarm Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
5h = Maximum value
11-8AMINLOWBCDR/W0h Alarm Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7AMINAEBINR/W0h Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
6RESERVEDR0h
5-0AMINBINR/W0h Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
3Bh = Maximum value

27.4.34 A1HOUR (Offset = 1134h) [Reset = 00000000h]

A1HOUR is shown in Figure 27-38 and described in Table 27-40.

Return to the Summary Table.

RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format

Figure 27-38 A1HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHOURAEBCDRESERVEDAHOURHIGHBCDAHOURLOWBCD
R/W-0hR-0hR/W-0hR/W-0h
76543210
AHOURAEBINRESERVEDAHOURBIN
R/W-0hR-0hR/W-0h
Table 27-40 A1HOUR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AHOURAEBCDR/W0h Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14RESERVEDR0h
13-12AHOURHIGHBCDR/W0h Alarm Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0..
0h = Minimum value
2h = Maximum value
11-8AHOURLOWBCDR/W0h Alarm Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7AHOURAEBINR/W0h Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
6-5RESERVEDR0h
4-0AHOURBINR/W0h Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
17h = Maximum value

27.4.35 A1DAY (Offset = 1138h) [Reset = 00000000h]

A1DAY is shown in Figure 27-39 and described in Table 27-41.

Return to the Summary Table.

RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format

Figure 27-39 A1DAY
3130292827262524
RESERVED
R-0h
2322212019181716
ADOMAEBCDRESERVEDADOMHIGHBCDADOMLOWBCD
R/W-0hR-0hR/W-0hR/W-0h
15141312111098
ADOMAEBINRESERVEDADOMBIN
R/W-0hR-0hR/W-0h
76543210
ADOWAERESERVEDADOW
R/W-0hR-0hR/W-0h
Table 27-41 A1DAY Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23ADOMAEBCDR/W0h Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
22RESERVEDR0h
21-20ADOMHIGHBCDR/W0h Alarm Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
3h = Maximum value
19-16ADOMLOWBCDR/W0h Alarm Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
15ADOMAEBINR/W0h Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14-13RESERVEDR0h
12-8ADOMBINR/W0h Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
1Fh = Maximum value
7ADOWAER/W0h Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0.
0h = Alarm disabled
1h = Alarm enabled
6-3RESERVEDR0h
2-0ADOWR/W0h Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Minimum value
6h = Maximum value

27.4.36 A2MIN (Offset = 113Ch) [Reset = 00000000h]

A2MIN is shown in Figure 27-40 and described in Table 27-42.

Return to the Summary Table.

RTC Minutes Alarm Register - Calendar Mode With Binary / BCD Format

Figure 27-40 A2MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AMINAEBCDAMINHIGHBCDAMINLOWBCD
R/W-0hR/W-0hR/W-0h
76543210
AMINAEBINRESERVEDAMINBIN
R/W-0hR-0hR/W-0h
Table 27-42 A2MIN Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AMINAEBCDR/W0h Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14-12AMINHIGHBCDR/W0h Alarm Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
5h = Maximum value
11-8AMINLOWBCDR/W0h Alarm Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7AMINAEBINR/W0h Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
6RESERVEDR0h
5-0AMINBINR/W0h Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
3Bh = Maximum value

27.4.37 A2HOUR (Offset = 1140h) [Reset = 00000000h]

A2HOUR is shown in Figure 27-41 and described in Table 27-43.

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RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format

Figure 27-41 A2HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHOURAEBCDRESERVEDAHOURHIGHBCDAHOURLOWBCD
R/W-0hR-0hR/W-0hR/W-0h
76543210
AHOURAEBINRESERVEDAHOURBIN
R/W-0hR-0hR/W-0h
Table 27-43 A2HOUR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AHOURAEBCDR/W0h Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14RESERVEDR0h
13-12AHOURHIGHBCDR/W0h Alarm Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0..
0h = Minimum value
2h = Maximum value
11-8AHOURLOWBCDR/W0h Alarm Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
7AHOURAEBINR/W0h Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
6-5RESERVEDR0h
4-0AHOURBINR/W0h Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
17h = Maximum value

27.4.38 A2DAY (Offset = 1144h) [Reset = 00000000h]

A2DAY is shown in Figure 27-42 and described in Table 27-44.

Return to the Summary Table.

RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format

Figure 27-42 A2DAY
3130292827262524
RESERVED
R-0h
2322212019181716
ADOMAEBCDRESERVEDADOMHIGHBCDADOMLOWBCD
R/W-0hR-0hR/W-0hR/W-0h
15141312111098
ADOMAEBINRESERVEDADOMBIN
R/W-0hR-0hR/W-0h
76543210
ADOWAERESERVEDADOW
R/W-0hR-0hR/W-0h
Table 27-44 A2DAY Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23ADOMAEBCDR/W0h Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
22RESERVEDR0h
21-20ADOMHIGHBCDR/W0h Alarm Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
3h = Maximum value
19-16ADOMLOWBCDR/W0h Alarm Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Minimum value
9h = Maximum value
15ADOMAEBINR/W0h Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored.
0h = Alarm disabled
1h = Alarm enabled
14-13RESERVEDR0h
12-8ADOMBINR/W0h Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Minimum value
1Fh = Maximum value
7ADOWAER/W0h Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0.
0h = Alarm disabled
1h = Alarm enabled
6-3RESERVEDR0h
2-0ADOWR/W0h Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Minimum value
6h = Maximum value

27.4.39 PSCTL (Offset = 1148h) [Reset = 00000008h]

PSCTL is shown in Figure 27-43 and described in Table 27-45.

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RTC Prescale Timer 0/1 Control Register

Figure 27-43 PSCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRT1IPRESERVED
R-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRT0IPRESERVED
R-0hR/W-2hR-0h
Table 27-45 PSCTL Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20-18RT1IPR/W0hPrescale timer 1 interrupt interval
0h = Divide by 2 - 15.6 millisecond interval
1h = Divide by 4 - 31.2 millisecond interval
2h = Divide by 8 - 62.5 millisecond interval
3h = Divide by 16 - 125 millisecond interval
4h = Divide by 32 - 250 millisecond interval
5h = Divide by 64 - 500 millisecond interval
6h = Divide by 128 - 1 second interval
7h = Divide by 256 - 2 second interval
17-5RESERVEDR0h
4-2RT0IPR/W2hPrescale timer 0 interrupt interval
2h = Divide by 8 - 244 microsecond interval
3h = Divide by 16 - 488 microsecond interval
4h = Divide by 32 - 976 microsecond interval
5h = Divide by 64 - 1.95 millisecond interval
6h = Divide by 128 - 3.90 millisecond interval
7h = Divide by 256 - 7.81 millisecond interval
1-0RESERVEDR0h

27.4.40 EXTPSCTL (Offset = 114Ch) [Reset = 00000000h]

EXTPSCTL is shown in Figure 27-44 and described in Table 27-46.

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Extended Prescale Timer Control Register

Figure 27-44 EXTPSCTL
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRT2PSRESERVED
R-0hR/W-0hR-0h
Table 27-46 EXTPSCTL Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-2RT2PSR/W0hPrescale timer 2 interrupt interval
0h = Interval every 4 second
1h = Interval every 8 second
2h = Interval every 16 second
1-0RESERVEDR0h

27.4.41 TSSEC (Offset = 1150h) [Reset = 00000000h]

TSSEC is shown in Figure 27-45 and described in Table 27-47.

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RTC Second Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-45 TSSEC
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSECHIGHBCDSECLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDSECBIN
R-0hR-0h
Table 27-47 TSSEC Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12SECHIGHBCDR0hTime Stamp Seconds BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8SECLOWBCDR0hTime Stamp Seconds BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0SECBINR0hTime Stamp Second Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

27.4.42 TSMIN (Offset = 1154h) [Reset = 00000000h]

TSMIN is shown in Figure 27-46 and described in Table 27-48.

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RTC Minutes Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-46 TSMIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMINHIGHBCDMINLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDMINBIN
R-0hR-0h
Table 27-48 TSMIN Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12MINHIGHBCDR0hTime Stamp Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8MINLOWBCDR0hTime Stamp Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0MINBINR0hTime Stamp Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3Bh = Highest possible value

27.4.43 TSHOUR (Offset = 1158h) [Reset = 00000000h]

TSHOUR is shown in Figure 27-47 and described in Table 27-49.

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RTC Hours Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-47 TSHOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDHOURHIGHBCDHOURLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDHOURBIN
R-0hR-0h
Table 27-49 TSHOUR Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h
13-12HOURHIGHBCDR0hTime Stamp Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
00h = Smallest value
02h = Highest possible value
11-8HOURLOWBCDR0hTime Stamp Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
00h = Smallest value
09h = Highest possible value
7-5RESERVEDR0h
4-0HOURBINR0hTime Stamp Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
17h = Highest possible value

27.4.44 TSDAY (Offset = 115Ch) [Reset = 00000000h]

TSDAY is shown in Figure 27-48 and described in Table 27-50.

Return to the Summary Table.

RTC Day Of Week / Month Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-48 TSDAY
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDOMHIGHBCDDOMLOWBCD
R-0hR-0hR-0h
15141312111098
RESERVEDDOMBIN
R-0hR-0h
76543210
RESERVEDDOW
R-0hR-0h
Table 27-50 TSDAY Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-20DOMHIGHBCDR0hTime Stamp Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3h = Highest possible value
19-16DOMLOWBCDR0hTime Stamp Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-13RESERVEDR0h
12-8DOMBINR0hTime Stamp Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
1Fh = Highest possible value
7-3RESERVEDR0h
2-0DOWR0hTime Stamp Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Smallest value
6h = Highest possible value

27.4.45 TSMON (Offset = 1160h) [Reset = 00000000h]

TSMON is shown in Figure 27-49 and described in Table 27-51.

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RTC Month Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-49 TSMON
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMONHIGHBCDMONLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDMONBIN
R-0hR-0h
Table 27-51 TSMON Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h
12MONHIGHBCDR0hTime Stamp Month BCD – high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
1h = Highest possible value
11-8MONLOWBCDR0hTime Stamp Month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-4RESERVEDR0h
3-0MONBINR0hTime Stamp Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Ch = Highest possible value

27.4.46 TSYEAR (Offset = 1164h) [Reset = 00000000h]

TSYEAR is shown in Figure 27-50 and described in Table 27-52.

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RTC Years Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 27-50 TSYEAR
3130292827262524
RESERVEDCENTHIGHBCDCENTLOWBCD
R-0hR-0hR-0h
2322212019181716
DECADEBCDYERARLOWESTBCD
R-0hR-0h
15141312111098
RESERVEDYEARHIGHBIN
R-0hR-0h
76543210
YEARLOWBIN
R-0h
Table 27-52 TSYEAR Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h
30-28CENTHIGHBCDR0hTime Stamp Century BCD – high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
4h = Highest possible value
27-24CENTLOWBCDR0hTime Stamp Century BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
23-20DECADEBCDR0hTime Stamp Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
19-16YERARLOWESTBCDR0hTime Stamp Year BCD – lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-12RESERVEDR0h
11-8YEARHIGHBINR0hTime Stamp Year Binary – high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Fh = Highest possible value
7-0YEARLOWBINR0hTime Stamp Year Binary – low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
FFh = Highest possible value

27.4.47 TSSTAT (Offset = 1168h) [Reset = 00000000h]

TSSTAT is shown in Figure 27-51 and described in Table 27-53.

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Time Stamp Status

Figure 27-51 TSSTAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTSVDDEVT
R-0hR-0h
15141312111098
TSTIOEVT15TSTIOEVT14TSTIOEVT13TSTIOEVT12TSTIOEVT11TSTIOEVT10TSTIOEVT9TSTIOEVT8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSTIOEVT7TSTIOEVT6TSTIOEVT5TSTIOEVT4TSTIOEVT3TSTIOEVT2TSTIOEVT1TSTIOEVT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-53 TSSTAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16TSVDDEVTR0hLoss of VDD caused time stamp event
0h = no event detected
1h = event detected
15TSTIOEVT15R0hTamper I/O 15 caused time stamp event
0h = no event detected
1h = event detected
14TSTIOEVT14R0hTamper I/O 14 caused time stamp event
0h = no event detected
1h = event detected
13TSTIOEVT13R0hTamper I/O 13 caused time stamp event
0h = no event detected
1h = event detected
12TSTIOEVT12R0hTamper I/O 12 caused time stamp event
0h = no event detected
1h = event detected
11TSTIOEVT11R0hTamper I/O 11 caused time stamp event
0h = no event detected
1h = event detected
10TSTIOEVT10R0hTamper I/O 10 caused time stamp event
0h = no event detected
1h = event detected
9TSTIOEVT9R0hTamper I/O 9 caused time stamp event
0h = no event detected
1h = event detected
8TSTIOEVT8R0hTamper I/O 8 caused time stamp event
0h = no event detected
1h = event detected
7TSTIOEVT7R0hTamper I/O 7 caused time stamp event
0h = no event detected
1h = event detected
6TSTIOEVT6R0hTamper I/O 6 caused time stamp event
0h = no event detected
1h = event detected
5TSTIOEVT5R0hTamper I/O 5 caused time stamp event
0h = no event detected
1h = event detected
4TSTIOEVT4R0hTamper I/O 4 caused time stamp event
0h = no event detected
1h = event detected
3TSTIOEVT3R0hTamper I/O 3 caused time stamp event
0h = no event detected
1h = event detected
2TSTIOEVT2R0hTamper I/O 2 caused time stamp event
0h = no event detected
1h = event detected
1TSTIOEVT1R0hTamper I/O 1 caused time stamp event
0h = no event detected
1h = event detected
0TSTIOEVT0R0hTamper I/O 0 caused time stamp event
0h = no event detected
1h = event detected

27.4.48 TSCTL (Offset = 116Ch) [Reset = 00000000h]

TSCTL is shown in Figure 27-52 and described in Table 27-54.

Return to the Summary Table.

time stamp control register

Figure 27-52 TSCTL
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVEDTSCAPTURERESERVEDTSVDDEN
R-0hR/WK-0hR-0hR/WK-0h
15141312111098
TSTIOEN15TSTIOEN14TSTIOEN13TSTIOEN12TSTIOEN11TSTIOEN10TSTIOEN9TSTIOEN8
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TSTIOEN7TSTIOEN6TSTIOEN5TSTIOEN4TSTIOEN3TSTIOEN2TSTIOEN1TSTIOEN0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 27-54 TSCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xC5) to update this register
C5h = This field must be written with 0xC5 to be able to clear any of the enable bits
23-21RESERVEDR0h
20TSCAPTURER/WK0hDefines the capture method of the RTC timestamp when a time stamp event occurs.

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = Time stamp holds RTC capture at first occurrence of time stamp event.
1h = Time stamp holds RTC capture at last occurrence of time stamp event.
19-17RESERVEDR0h
16TSVDDENR/WK0hTime Stamp by VDD Loss detection enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
15TSTIOEN15R/WK0hTime Stamp by Tamper I/O 15 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
14TSTIOEN14R/WK0hTime Stamp by Tamper I/O 14 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
13TSTIOEN13R/WK0hTime Stamp by Tamper I/O 13 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
12TSTIOEN12R/WK0hTime Stamp by Tamper I/O 12 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
11TSTIOEN11R/WK0hTime Stamp by Tamper I/O 11 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
10TSTIOEN10R/WK0hTime Stamp by Tamper I/O 10 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
9TSTIOEN9R/WK0hTime Stamp by Tamper I/O 9 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
8TSTIOEN8R/WK0hTime Stamp by Tamper I/O 8 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
7TSTIOEN7R/WK0hTime Stamp by Tamper I/O 7 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
6TSTIOEN6R/WK0hTime Stamp by Tamper I/O 6 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
5TSTIOEN5R/WK0hTime Stamp by Tamper I/O 5 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
4TSTIOEN4R/WK0hTime Stamp by Tamper I/O 4 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
3TSTIOEN3R/WK0hTime Stamp by Tamper I/O 3 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
2TSTIOEN2R/WK0hTime Stamp by Tamper I/O 2 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
1TSTIOEN1R/WK0hTime Stamp by Tamper I/O 1 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled
0TSTIOEN0R/WK0hTime Stamp by Tamper I/O 0 enable

[IPSPECIFIC_RTC.TSCTL.KEY] must be written to access this bit.


0h = function disabled
1h = function enabled

27.4.49 TSCLR (Offset = 1170h) [Reset = 00000000h]

TSCLR is shown in Figure 27-53 and described in Table 27-55.

Return to the Summary Table.

time stamp clear register

Figure 27-53 TSCLR
31302928272625242322212019181716
KEYRESERVED
R-0/W-0hR-0h
1514131211109876543210
RESERVEDCLR
R-0hWK-0h
Table 27-55 TSCLR Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE2) to update this register
E2h = This field must be written with 0xE2 to be able to clear any of the enable bits
23-1RESERVEDR0h
0CLRWK0hClear time stamp and status register.

[IPSPECIFIC_RTC.TSCLR.KEY] must be written to access this bit.


0h = Writing 0 has no effect
1h = clear time stamp event

27.4.50 LFSSRST (Offset = 1174h) [Reset = 00000000h]

LFSSRST is shown in Figure 27-54 and described in Table 27-56.

Return to the Summary Table.

Low frequency subsystem reset request. Asserting the VBATPOR bit in this register will issue a power cycle on the battery backup domain. This reset has the same effect as removing and reconnecting the power supply to the VBAT power pin.
This register can be write protected by the RTCLOCK register.

Figure 27-54 LFSSRST
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDVBATPOR
R-0hR/WK-0h
Table 27-56 LFSSRST Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0x12) to update this register
12h = This field must be written with 0x12 to be able to request the power on reset.
23-1RESERVEDR0h
0VBATPORR/WK0hIf set, the register bit will request a power on reset to the PMU of the LFSS.

[IPSPECIFIC_RTC.LFSSRST.KEY] must be written to access this bit.


0h = Writing this value has no effect.
1h = Request power on reset to the LFSS.

27.4.51 RTCLOCK (Offset = 1178h) [Reset = 00000000h]

RTCLOCK is shown in Figure 27-55 and described in Table 27-57.

Return to the Summary Table.

The RTC lock bit protects the CLKCTL, SEC, MIN, HOUR, DAY, MON, YEAR and LFSSRST registers from accidental updates.

Figure 27-55 RTCLOCK
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROTECT
R-0hR/WK-0h
Table 27-57 RTCLOCK Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0x22) to update this register
22h = This field must be written with 0x22 to be able to update any of the bits.
23-1RESERVEDR0h
0PROTECTR/WK0hIf set, the register bit will protect the CLKCTL, SEC, MIN, HOUR, DAY, MON, YEAR and LFSSRST from accidental writes.

[IPSPECIFIC_RTC.RTCLOCK.KEY] must be written to access this bit.


0h = RTC counter is writable.
1h = RTC counter is read only access.