SLAU847E October   2022  – May 2025 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 RTCCLK (RTC Clock)
        11. 2.3.2.11 External Clock Output (CLK_OUT)
        12. 2.3.2.12 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.5.7 Optimizing for Lowest Wakeup Latency
      8. 2.5.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Layout Types
    7. 2.7 SYSCTL_TYPEA Registers
    8. 2.8 SYSCTL_TYPEB Registers
    9. 2.9 SYSCTL_TYPEC Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 DMA
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AESADV
    1. 10.1 AESADV Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24Timers (TIMx)
    1. 24.1 TIMx Overview
      1. 24.1.1 TIMG Overview
        1. 24.1.1.1 TIMG Features
        2. 24.1.1.2 Functional Block Diagram
      2. 24.1.2 TIMA Overview
        1. 24.1.2.1 TIMA Features
        2. 24.1.2.2 Functional Block Diagram
      3. 24.1.3 TIMx Instance Configuration
    2. 24.2 TIMx Operation
      1. 24.2.1  Timer Counter
        1. 24.2.1.1 Clock Source Select and Prescaler
          1. 24.2.1.1.1 Internal Clock and Prescaler
          2. 24.2.1.1.2 External Signal Trigger
        2. 24.2.1.2 Repeat Counter (TIMA only)
      2. 24.2.2  Counting Mode Control
        1. 24.2.2.1 One-shot and Periodic Modes
        2. 24.2.2.2 Down Counting Mode
        3. 24.2.2.3 Up/Down Counting Mode
        4. 24.2.2.4 Up Counting Mode
        5. 24.2.2.5 Phase Load (TIMA only)
      3. 24.2.3  Capture/Compare Module
        1. 24.2.3.1 Capture Mode
          1. 24.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 24.2.3.1.1.1 CCP Input Edge Synchronization
            2. 24.2.3.1.1.2 CCP Input Pulse Conditions
            3. 24.2.3.1.1.3 Counter Control Operation
            4. 24.2.3.1.1.4 CCP Input Filtering
            5. 24.2.3.1.1.5 Input Selection
          2. 24.2.3.1.2 Use Cases
            1. 24.2.3.1.2.1 Edge Time Capture
            2. 24.2.3.1.2.2 Period Capture
            3. 24.2.3.1.2.3 Pulse Width Capture
            4. 24.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 24.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 24.2.3.1.3.1 QEI With 2-Signal
            2. 24.2.3.1.3.2 QEI With Index Input
            3. 24.2.3.1.3.3 QEI Error Detection
          4. 24.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 24.2.3.2 Compare Mode
          1. 24.2.3.2.1 Edge Count
      4. 24.2.4  Shadow Load and Shadow Compare
        1. 24.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 24.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 24.2.5  Output Generator
        1. 24.2.5.1 Configuration
        2. 24.2.5.2 Use Cases
          1. 24.2.5.2.1 Edge-Aligned PWM
          2. 24.2.5.2.2 Center-Aligned PWM
          3. 24.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 24.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 24.2.5.3 Forced Output
      6. 24.2.6  Fault Handler (TIMA only)
        1. 24.2.6.1 Fault Input Conditioning
        2. 24.2.6.2 Fault Input Sources
        3. 24.2.6.3 Counter Behavior With Fault Conditions
        4. 24.2.6.4 Output Behavior With Fault Conditions
      7. 24.2.7  Synchronization With Cross Trigger
        1. 24.2.7.1 Main Timer Cross Trigger Configuration
        2. 24.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 24.2.8  Low Power Operation
      9. 24.2.9  Interrupt and Event Support
        1. 24.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 24.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 24.2.10 Debug Handler (TIMA Only)
    3. 24.3 TIMx Registers
  27. 25Low Frequency Subsystem (LFSS)
    1. 25.1  Overview
    2. 25.2  Clock System
    3. 25.3  LFSS Reset Using VBAT
    4. 25.4  Power Domains and Supply Detection
      1. 25.4.1 Startup When VBAT Powers on First
      2. 25.4.2 Startup when VDD powers on first
      3. 25.4.3 Behavior When VDD is Lost
      4. 25.4.4 Behavior when VBAT is lost
      5. 25.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 25.4.6 Supercapacitor Charging Circuit
    5. 25.5  Real Time Counter (RTC_x)
    6. 25.6  Independent Watchdog Timer (IWDT)
    7. 25.7  Tamper Input and Output
      1. 25.7.1 IOMUX Mode
      2. 25.7.2 Tamper Mode
        1. 25.7.2.1 Tamper Event Detection
        2. 25.7.2.2 Timestamp Event Output
        3. 25.7.2.3 Heartbeat Generator
        4. 25.7.2.4 RTC Clock Output
    8. 25.8  Scratchpad Memory
    9. 25.9  Lock Function of RTC, TIO, and IWDT
    10. 25.10 LFSS Registers
  28. 26Low Frequency Subsystem (LFSS_B)
    1. 26.1 Overview
    2. 26.2 Clock System
    3. 26.3 LFSS Reset
    4. 26.4 Real Time Counter (RTC_x)
    5. 26.5 Independent Watchdog Timer (IWDT)
    6. 26.6 Lock Function of RTC and IWDT
    7. 26.7 LFSS Registers
  29. 27RTC
    1. 27.1 Overview
      1. 27.1.1 RTC Instances
    2. 27.2 Basic Operation
    3. 27.3 Configuration
      1. 27.3.1  Clocking
      2. 27.3.2  Reading and Writing to RTC Peripheral Registers
      3. 27.3.3  Binary vs. BCD
      4. 27.3.4  Leap Year Handling
      5. 27.3.5  Calendar Alarm Configuration
      6. 27.3.6  Interval Alarm Configuration
      7. 27.3.7  Periodic Alarm Configuration
      8. 27.3.8  Calibration
        1. 27.3.8.1 Crystal Offset Error
          1. 27.3.8.1.1 Offset Error Correction Mechanism
        2. 27.3.8.2 Crystal Temperature Error
          1. 27.3.8.2.1 Temperature Drift Correction Mechanism
      9. 27.3.9  RTC Prescaler Extension
      10. 27.3.10 RTC Timestamp Capture
      11. 27.3.11 RTC Events
        1. 27.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 27.4 RTC Registers
  30. 28IWDT
    1. 28.1 734
    2. 28.2 IWDT Clock Configuration
    3. 28.3 IWDT Period Selection
    4. 28.4 Debug Behavior of the IWDT
    5. 28.5 IWDT Registers
  31. 29WWDT
    1. 29.1 WWDT Overview
      1. 29.1.1 Watchdog Mode
      2. 29.1.2 Interval Timer Mode
    2. 29.2 WWDT Operation
      1. 29.2.1 Mode Selection
      2. 29.2.2 Clock Configuration
      3. 29.2.3 Low-Power Mode Behavior
      4. 29.2.4 Debug Behavior
      5. 29.2.5 WWDT Events
        1. 29.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 29.3 WWDT Registers
  32. 30Debug
    1. 30.1 DEBUGSS Overview
      1. 30.1.1 Debug Interconnect
      2. 30.1.2 Physical Interface
      3. 30.1.3 Debug Access Ports
    2. 30.2 DEBUGSS Operation
      1. 30.2.1 Debug Features
        1. 30.2.1.1 Processor Debug
          1. 30.2.1.1.1 Breakpoint Unit (BPU)
          2. 30.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 30.2.1.2 Peripheral Debug
        3. 30.2.1.3 EnergyTrace Technology
      2. 30.2.2 Behavior in Low Power Modes
      3. 30.2.3 Restricting Debug Access
      4. 30.2.4 Mailbox (DSSM)
        1. 30.2.4.1 DSSM Events
          1. 30.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 30.2.4.2 Reference
    3. 30.3 DEBUGSS Registers
  33. 31Revision History

13.3 TRNG Registers

Table 13-6 lists the memory-mapped registers for the TRNG registers. All register offset addresses not listed in Table 13-6 should be considered as reserved locations and the register contents should not be modified.

Table 13-6 TRNG Registers
OffsetAcronymRegister NameGroupSection
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
10FChDESCModule descriptionsGo
1100hCTLControls the command and decimation rateGo
1104hSTATStatus register that informs health test results and last issued commandGo
1108hDATA_CAPTURECaptured word buffer of RNG dataGo
110ChTEST_RESULTSTest results from TEST_ANA and TEST_DIGGo
1110hCLKDIVIDEClock DividerGo

Complex bit access types are encoded to fit into small table cells. Table 13-7 shows the codes that are used for access types in this section.

Table 13-7 TRNG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

13.3.1 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 13-3 and described in Table 13-8.

Return to the Summary Table.

Register to control the power state

Figure 13-3 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 13-8 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

13.3.2 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 13-4 and described in Table 13-9.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 13-4 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 13-9 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

13.3.3 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 13-5 and described in Table 13-10.

Return to the Summary Table.

peripheral enable and reset status

Figure 13-5 STAT
3130292827262524
RESERVED
R-
2322212019181716
RESERVEDRESETSTKY
R-R-0h
15141312111098
RESERVED
R-
76543210
RESERVED
R-
Table 13-10 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

13.3.4 IIDX (Offset = 1020h) [Reset = X]

IIDX is shown in Figure 13-6 and described in Table 13-11.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. 0h means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, … 231 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0h.

Figure 13-6 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-XR-0h
Table 13-11 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0STATR0hInterrupt index status
0h = No bit is set means there is no pending interrupt request
1h = Indicates that a health test has failed. The TRNG is in an error state until the interrupt is cleared.
2h = Indicates that the just issued command was rejected and is not being performed.
3h = Indicates that the current command/mode is done. This may have different meanings based on the mode:
OFF --> Power has been turned off
PWRUP_DIG --> Digital powerup tests are done
PWRUP_ANA --> Analog powerup tests are done
NORM_FUNC --> No IRQ, since mode runs indefinitely until a new command is issued
4h = Indicates that the captured word buffer is ready to be copied to memory

13.3.5 IMASK (Offset = 1028h) [Reset = X]

IMASK is shown in Figure 13-7 and described in Table 13-12.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt mask is set.

Figure 13-7 IMASK
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDIRQ_CAPTURED_RDYIRQ_CMD_DONEIRQ_CMD_FAILIRQ_HEALTH_FAIL
R/W-XR/W-0hR/W-0hR/W-0hR/W-0h
Table 13-12 IMASK Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3IRQ_CAPTURED_RDYR/W0hMask for IRQ_CAPTURED_RDY. Indicates to the CPU that the Captured Word is ready to be read.
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
2IRQ_CMD_DONER/W0hMask for IRQ_CMD_DONE. Indicates that a command has finished
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
1IRQ_CMD_FAILR/W0hMasked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
0IRQ_HEALTH_FAILR/W0hMask for IRQ_HEALTH_FAIL. Indicates that a health test has failed.
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set

13.3.6 RIS (Offset = 1030h) [Reset = X]

RIS is shown in Figure 13-8 and described in Table 13-13.

Return to the Summary Table.

Raw interrupt status reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 13-8 RIS
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDIRQ_CAPTURED_RDYIRQ_CMD_DONEIRQ_CMD_FAILIRQ_HEALTH_FAIL
R-XR-0hR-0hR-0hR-0h
Table 13-13 RIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3IRQ_CAPTURED_RDYR0hIndicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not occur
1h = IRQ_CAPTURED_READY occurred
2IRQ_CMD_DONER0hRaw interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed.
0h = IRQ_CMD_DONE did not occur
1h = IRQ_CMD_DONE occurred
1IRQ_CMD_FAILR0hMasked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = IRQ_CMD_FAIL did not occur
1h = IRQ_CMD_FAIL occurred
0IRQ_HEALTH_FAILR0hIndicates to the CPU that any of the health tests have failed. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not occur
1h = IRQ_CAPTURED_READY occurred

13.3.7 MIS (Offset = 1038h) [Reset = X]

MIS is shown in Figure 13-9 and described in Table 13-14.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 13-9 MIS
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDIRQ_CAPTURED_RDYIRQ_CMD_DONEIRQ_CMD_FAILIRQ_HEALTH_FAIL
R-XR-0hR-0hR-0hR-0h
Table 13-14 MIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3IRQ_CAPTURED_RDYR0hMasked interrupt result for CAPTURED_READY. Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine
1h = IRQ_CAPTURED_READY requests an interrupt service routine
2IRQ_CMD_DONER0hMasked interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine
1h = IRQ_CMD_DONE requests an interrupt service routine
1IRQ_CMD_FAILR0hMasked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = IRQ_CMD_FAIL did not request an interrupt service routine
1h = IRQ_CMD_FAIL requests an interrupt service routine
0IRQ_HEALTH_FAILR0hMasked interrupt result for HEALTH_FAIL. Indicates to the CPU that any of the health tests have failed for the latest 1024-bit window.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine
1h = IRQ_CAPTURED_READY requests an interrupt service routine

13.3.8 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 13-10 and described in Table 13-15.

Return to the Summary Table.

ISET allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 13-10 ISET
3130292827262524
RESERVED
W-
2322212019181716
RESERVED
W-
15141312111098
RESERVED
W-
76543210
RESERVEDIRQ_CAPTURED_RDYIRQ_CMD_DONEIRQ_CMD_FAILIRQ_HEALTH_FAIL
W-W-W-W-W-
Table 13-15 ISET Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3IRQ_CAPTURED_RDYW0hIndicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect
1h = RIS bit corresponding to CAPTURED_READY is set
2IRQ_CMD_DONEW0hWrite to turn on CMD_DONE IRQ. Indicates that the last issued TRNG command has finished.
0h = Writing a 0 has no effect.
1h = RIS bit corresponding to CMD_DONE is set
1IRQ_CMD_FAILW0hMasked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Writing a 0 has no effect.
1h = RIS bit corresponding to CMD_FAIL is set
0IRQ_HEALTH_FAILW0hIndicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect
1h = RIS bit corresponding to HEALTH_FAIL is set

13.3.9 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 13-11 and described in Table 13-16.

Return to the Summary Table.

Write a 1 to clear corresponding Interrupt.

Figure 13-11 ICLR
3130292827262524
RESERVED
W-
2322212019181716
RESERVED
W-
15141312111098
RESERVED
W-
76543210
RESERVEDIRQ_CAPTURED_RDYIRQ_CMD_DONEIRQ_CMD_FAILIRQ_HEALTH_FAIL
W-W-W-W-W-
Table 13-16 ICLR Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3IRQ_CAPTURED_RDYW0hIndicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect
1h = RIS bit corresponding to CAPTURED_READY is cleared
2IRQ_CMD_DONEW0hWrite to turn off CMD_DONE IRQ. Indicates that the last issued TRNG command has finished.
0h = Writing a 0 has no effect.
1h = RIS bit corresponding to CMD_DONE is cleared
1IRQ_CMD_FAILW0hMasked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Writing a 0 has no effect.
1h = RIS bit corresponding to CMD_FAIL is cleared
0IRQ_HEALTH_FAILW0hIndicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect
1h = RIS bit corresponding to CAPTURED_READY is cleared

13.3.10 DESC (Offset = 10FCh) [Reset = 05110000h]

DESC is shown in Figure 13-12 and described in Table 13-17.

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This register is used to specify clock source selection for any special modules that need to choose between MCLK and another special clock source. The register is not expected to be present on most standard SVT peripherals but may be present on modules such as the ADC. The register is not present on VDDCOREULP domain peripherals and will be reserved, reading 0.

Figure 13-12 DESC
31302928272625242322212019181716
MODULEID
R-511h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 13-17 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR511hModule Identifier - An internal TI page has been created to request unique module IDs
15-12FEATUREVERR0hFeature Set for the module *instance*
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
7-4MAJREVR0hMajor rev of the IP
3-0MINREVR0hMinor rev of the IP

13.3.11 CTL (Offset = 1100h) [Reset = X]

CTL is shown in Figure 13-13 and described in Table 13-18.

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Affects various parameters of the TRNG system

Figure 13-13 CTL
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPWRUP_PSTART_CFGPWRUP_PCHRG_CFGPWRUP_CLKDIV
R/W-XR/W-2hR/W-2hR/W-0h
15141312111098
RESERVEDDECIM_RATE
R/W-XR/W-0h
76543210
RESERVEDCMD
R/W-XR/W-0h
Table 13-18 CTL Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-19PWRUP_PSTART_CFGR/W2hConfigure pulse startup sequence length

b00 = Disabled
b01 = rise at 10us, fall at 50us
b10 = rise at 10us, fall at 70us (default)
b11 = rise at 10us, fall at 90us
18-17PWRUP_PCHRG_CFGR/W2hConfigure PCHARGE sequence length

b00 = Disabled
b01 = 20 us PCHARGE
b10 = 30 us PCHARGE (default)
b11 = 40 us PCHARGE
16PWRUP_CLKDIVR/W0hWhen '1', the power-up sequence takes twice as long (clock frequency halved)
15-11RESERVEDR/WX
10-8DECIM_RATER/W0hSet decimation rate. Decimate by n
0x0 = Decimation by 1 (no decimation)
0x1 = Decimation by 2 (Skip every other sample)
…
0x7 = Decimation by 8 (Take every 8th sample)
7-2RESERVEDR/WX
1-0CMDR/W0hSets the TRNG mode through a command. The mode will not be updated until the previous command is done, as indicated by IRQ_CMD_DONE.
00 --> OFF
01 --> PWRUP_DIG
10 --> PWRUP_ANA
11 --> NORM_FUNC
0h = Turns the power off of the analog source and clocks the digital interface
1h = Initiates the powerup test sequence for the digital components. This verifies that the digital components are properly working. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bits 0:6 in TEST_RESULTS register
2h = Initiates the powerup test sequence for the analog TRNG. This verifies that the analog component is generating sequences with enough entropy. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bit 7 in TEST_RESULTS register
3h = Normal operating mode for TRNG. All components are turned on.

13.3.12 STAT (Offset = 1104h) [Reset = X]

STAT is shown in Figure 13-14 and described in Table 13-19.

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Status register that informs health test result, last issued command, and current FSM state

Figure 13-14 STAT
3130292827262524
RESERVED
R-X
2322212019181716
RESERVEDFSM_STATE
R-XR-0h
15141312111098
RESERVEDISSUED_CMD
R-XR-0h
76543210
RESERVEDREP_FAILADAP_FAIL
R-XR-0hR-0h
Table 13-19 STAT Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDRX
19-16FSM_STATER0hCurrent state of the front end FSM (behind a clock domain crossing).
2 reads are REQUIRED as there is a chance of metastability when reading this
States:
0000: OFF
0001: PWRUP_ES
0011: NORM_FUNC
0111: TEST_DIG
1011: TEST_ANA
1010: ERROR
0010: PWRDOWN_ES
15-10RESERVEDRX
9-8ISSUED_CMDR0hIndicates the last accepted command that is issued to the TRNG interface.
Upon writing a valid command, this register will update and the command will be in progress until CMD_DONE_IRQ is set.
CMD_DONE_IRQ indicates that the state is in PWROFF, NORM_FUNC, or ERROR. These states will accept new commands.
00 --> OFF
01 --> PWRUP_DIG
10 --> PWRUP_ANA
11 --> NORM_FUNC
7-2RESERVEDRX
1REP_FAILR0hIndicates that the repetition counter test caused the most recent failure. Thus, the health count numbers are most likely not for a complete 1024-bit window.
0ADAP_FAILR0hIndicates that the Adaptive Proportion Test (1,2,3, or 4-bit counters) failed by having too many or too few counted samples in the last 1024 bit window.

13.3.13 DATA_CAPTURE (Offset = 1108h) [Reset = 00000000h]

DATA_CAPTURE is shown in Figure 13-15 and described in Table 13-20.

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Captured data from decimation block

Figure 13-15 DATA_CAPTURE
313029282726252423222120191817161514131211109876543210
BUFFER
R-0h
Table 13-20 DATA_CAPTURE Field Descriptions
BitFieldTypeResetDescription
31-0BUFFERR0hCaptured Data from the Decimation Block

13.3.14 TEST_RESULTS (Offset = 110Ch) [Reset = X]

TEST_RESULTS is shown in Figure 13-16 and described in Table 13-21.

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Includes a bit describing which startup test failed. The first 8 bits check the condition of the digital components in the digital startup validation check and the 9th bit checks that the entropy source is producing samples that have enough entropy. This register will read all '0s when a command is not finished. Each of the tests are active low, indicating a failed test with '0' and a passed test with '1'.

Figure 13-16 TEST_RESULTS
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDANA_TEST
R-XR-0h
76543210
DIG_TEST
R-0h
Table 13-21 TEST_RESULTS Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDRX
8ANA_TESTR0hRuns through 4096 samples from an enabled entropy source and verifies that none of the health tests failed, indicating sufficient entropy was produced by the analog components
7-0DIG_TESTR0hBit 0 indicates if the first decimation rate test and health test(verifies conditioning, decimation, and captured buffer) fails and Bit 1 indicates if the second decimation test and health test fails
Bit 0 - decim_test0 (decim = 0x0)
Bit 1 - decim_test1 (decim = 0x1) ...

13.3.15 CLKDIVIDE (Offset = 1110h) [Reset = 00000000h]

CLKDIVIDE is shown in Figure 13-17 and described in Table 13-22.

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This register is used to specify module-specific divide ratio of the functional clock and it only supports even division for TRNG.

Figure 13-17 CLKDIVIDE
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRATIO
R/W-0hR/W-0h
Table 13-22 CLKDIVIDE Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0RATIOR/W0hSelects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
3h = Divide clock source by 4
5h = Divide clock source by 6
7h = Divide clock source by 8