SPRAD05E August   2024  – October 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Processor Support for Secure Boot and Functional Safety
      2. 1.4.2 Note on AM625SIP Processor Data Sheet
      3. 1.4.3 AM625 and AM625SIP Custom Boards, Design Compatibility
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated SK Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Supported Low-Power Modes
        1. 3.2.1.1 Partial IO Support for CAN/GPIO/UART Wakeup
      2. 3.2.2 Core Power Supply
      3. 3.2.3 Peripherals Power Supply
      4. 3.2.4 DDR PHY and SDRAM Power Supply
        1. 3.2.4.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
        2. 3.2.4.2 AM625SIP
      5. 3.2.5 Dual-Voltage IO Supply for IO Group (Processor) Power Supply
      6. 3.2.6 Dynamic Voltage Switching Dual-Voltage Power Supply
      7. 3.2.7 VPP (eFuse ROM Programming) Power Supply
      8. 3.2.8 Internal LDOs for IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 3.4.2 AM625SIP
      3. 3.4.3 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Using Processor Supported External Input Voltage Monitors)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 WKUP_LFOSC0 Connection When Unused
      2. 4.1.2 MCU_OSC0 and WKUP_LFOSC0, Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Outputs
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Device
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores and MCU Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
        1. 7.3.1.1 Processor DDR Subsystem and Device Register Configuration
        2. 7.3.1.2 Calibration Resistor Connection for DDRSS
        3. 7.3.1.3 DDRSS Signals Pin (Package) Delay Information
        4. 7.3.1.4 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
      2. 7.3.2 AM625SIP
        1. 7.3.2.1 AMK Package Reassigned DDRSS Pins
        2. 7.3.2.2 DDRSS and Memory Device Calibration Resistor Connection
        3. 7.3.2.3 LPDDR4 (Internal) Memory Calibration Resistor Connection
    4. 7.4  Media and Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
    6. 7.6  Programmable Real-Time Unit Subsystem (PRUSS)
    7. 7.7  Universal Serial Bus (USB) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Display Subsystem (DSS)
      1. 7.9.1 AM625 / AM623 / AM625-Q1 / AM625SIP
      2. 7.9.2 AM620-Q1
    10. 7.10 CSI-Rx (Camera Serial interface)
    11. 7.11 Real-Time Clock (RTC) Module
    12. 7.12 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.12.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 7.12.2 AM625SIP
      3. 7.12.3 External Interrupt (EXTINTn)
      4. 7.12.4 RSVD Reserved Pins (Signals)
    13. 7.13 SK Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Supported Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Design and Layout Guidelines
      1. 11.2.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 11.2.2 AM625SIP
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Processor-Specific SK Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 11.5.2 AM625SIP
      3. 11.5.3 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14References
    1. 14.1 AM625SIP
    2. 14.2 AM625 / AM623
    3. 14.3 AM620-Q1 / AM625-Q1
    4. 14.4 AM625 / AM623 / AM620-Q1 / AM625-Q1
    5. 14.5 Common for all AM62x family of processors
  18. 15Terminology
  19. 16Revision History

2.2 Configuring the Boot Mode

The recommendation is to indicate the configured boot mode and the boot mode provisions provided in the block diagram including primary boot and backup boot.

For supported boot mode configurations, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 / AM62L - Supported bootmode configurations

The processor family supports multiple peripheral interfaces that support boot. For the available boot mode configurations and supported peripherals, see the device-specific TRM. The processor family supports primary boot mode and an optional backup boot mode configuration. If the primary boot (source) mode fails, the ROM switches on to the backup boot mode.

Boot mode configuration to be used (by the ROM code) during boot are set by the boot mode configuration (pullup or pulldown) resistors connected to the processor boot mode inputs directly (or through external buffers). The BOOTMODE [15:0] pin configurations (level) are latched into the Device Status register CTRLMMR_MAIN_DEVSTAT[15:0] as the processor comes out of cold reset, sampled after MCU_PORz input deassertion (rising edge of PORz_OUT output (buffered output of MCU_PORz input)). The boot mode configuration inputs are recommended to be stable before releasing (deassertion) the MCU_PORz input.

Processor boot mode can be configured using discrete (parallel pull) resistors for the below boot configuration (functionality):

PLL Config (Configuration): BOOTMODE [02:00] – PLL config pins are used to indicate the system clock (PLL reference clock selection) frequency (MCU_OSC0_XI/XO) to ROM code for PLL configuration

Note:

For supported crystal frequency see the processor-specific data sheet. Configure the boot mode to match the supported crystal or clock frequency. Wrong clock frequency configuration affects the processor performance including resetting of the board.

Primary Boot Mode: BOOTMODE [06:03] – The boot mode pins are used to configure the required primary boot mode, i.e, the peripheral/memory to boot from

Primary Boot Mode Config: BOOTMODE [09:07] – The boot mode configuration pins support optional configurations for primary boot and are used in conjunction with the primary boot mode selection pins

Backup Boot Mode: BOOTMODE [12:10] – The boot mode pins are used to configure the required backup boot mode, i.e., the peripheral/memory to boot from, in case primary boot fails

Backup Boot Mode Config: BOOTMODE [13] – The boot mode pin provides additional configuration options (optional - depends on the selected backup boot mode pins)

Reserved: BOOTMODE [15:14] – Reserved pins (The recommendation is to not leave the reserved pins unconnected)

Note: Leaving BOOTMODE [15:00] pins unconnected is not recommended or allowed option.

Key considerations when configuring boot mode:

  • The recommendation is to always include provision to configure boot modes used during the custom board development phase, such as USB boot (USB0, DFU), UART boot (UART0) or no-boot/Dev boot mode for debug (using JTAG)
  • Boot mode pins support alternate functions that can be configured after the boot mode configuration inputs are latched. The recommendation is to take into consideration the alternate function implemented when choosing pullup or pulldown resistors during custom board design. In case the boot mode inputs are being driven by external inputs to support test automation or remote configuration, the boot mode inputs are required to return to the required boot configuration value (level) whenever the processor is reset (indicated by the PORz_OUT output pin) to allow the processor to boot correctly.
  • Some of the boot mode pins functionalities are reserved. Boot mode pins marked as Reserved or not used are not recommended or allowed to be unconnected (float). The recommendation is to pull the input high or low using an external resistor. For information regarding connection of reserved boot mode pins, see the BOOTMODE Pin Mapping section of the Initialization chapter of the device-specific TRM.

For information related to supported boot modes, see the Initialization chapter of the device-specific TRM and device-specific silicon errata.

Note:

Custom board designers are responsible for providing provision to set the required boot mode configuration (using pullups or pulldowns, or optionally using jumpers/switches (with provision for external ESD protection when set in uncontrolled ESD environment)). The recommendation is to provide provision for pullup and pulldown for the boot mode input pins that have configuration capability for increase design flexibility. Shorting of multiple boot mode input pins together, leaving any of the boot mode input pins unconnected or connecting the boot mode inputs directly to supply or ground is not recommended or allowed.

Note:

The recommendation is to connect the processor boot mode input pins (configured for alternate function) to the alternate function through a 0Ω series resistor. Series resistor can be used to isolate the alternate function during testing.

For implementing the boot mode, see the following FAQs:

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62A / AM62P / AM62D-Q1 / AM62L - Bootmode implementation with isolation buffers used

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62A / AM62P / AM62D-Q1 / AM62L - Bootmode implementation without isolation buffers