SPRAD05E August   2024  – October 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Processor Support for Secure Boot and Functional Safety
      2. 1.4.2 Note on AM625SIP Processor Data Sheet
      3. 1.4.3 AM625 and AM625SIP Custom Boards, Design Compatibility
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated SK Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Supported Low-Power Modes
        1. 3.2.1.1 Partial IO Support for CAN/GPIO/UART Wakeup
      2. 3.2.2 Core Power Supply
      3. 3.2.3 Peripherals Power Supply
      4. 3.2.4 DDR PHY and SDRAM Power Supply
        1. 3.2.4.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
        2. 3.2.4.2 AM625SIP
      5. 3.2.5 Dual-Voltage IO Supply for IO Group (Processor) Power Supply
      6. 3.2.6 Dynamic Voltage Switching Dual-Voltage Power Supply
      7. 3.2.7 VPP (eFuse ROM Programming) Power Supply
      8. 3.2.8 Internal LDOs for IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 3.4.2 AM625SIP
      3. 3.4.3 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Using Processor Supported External Input Voltage Monitors)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 WKUP_LFOSC0 Connection When Unused
      2. 4.1.2 MCU_OSC0 and WKUP_LFOSC0, Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Outputs
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Device
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores and MCU Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
        1. 7.3.1.1 Processor DDR Subsystem and Device Register Configuration
        2. 7.3.1.2 Calibration Resistor Connection for DDRSS
        3. 7.3.1.3 DDRSS Signals Pin (Package) Delay Information
        4. 7.3.1.4 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
      2. 7.3.2 AM625SIP
        1. 7.3.2.1 AMK Package Reassigned DDRSS Pins
        2. 7.3.2.2 DDRSS and Memory Device Calibration Resistor Connection
        3. 7.3.2.3 LPDDR4 (Internal) Memory Calibration Resistor Connection
    4. 7.4  Media and Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
    6. 7.6  Programmable Real-Time Unit Subsystem (PRUSS)
    7. 7.7  Universal Serial Bus (USB) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Display Subsystem (DSS)
      1. 7.9.1 AM625 / AM623 / AM625-Q1 / AM625SIP
      2. 7.9.2 AM620-Q1
    10. 7.10 CSI-Rx (Camera Serial interface)
    11. 7.11 Real-Time Clock (RTC) Module
    12. 7.12 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.12.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 7.12.2 AM625SIP
      3. 7.12.3 External Interrupt (EXTINTn)
      4. 7.12.4 RSVD Reserved Pins (Signals)
    13. 7.13 SK Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Supported Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Design and Layout Guidelines
      1. 11.2.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 11.2.2 AM625SIP
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Processor-Specific SK Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 AM625 / AM623 / AM620-Q1 / AM625-Q1
      2. 11.5.2 AM625SIP
      3. 11.5.3 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14References
    1. 14.1 AM625SIP
    2. 14.2 AM625 / AM623
    3. 14.3 AM620-Q1 / AM625-Q1
    4. 14.4 AM625 / AM623 / AM620-Q1 / AM625-Q1
    5. 14.5 Common for all AM62x family of processors
  18. 15Terminology
  19. 16Revision History

7.7 Universal Serial Bus (USB) Subsystem

The processor family supports x2 (two) instances of USB 2.0 interface ports. The USB interfaces (USB0, USB1 ports) can be configured as host or device or Dual-Role Device (DRD). USBn_ID (identification) functionality can be implemented (supported) using any of the processor GPIO.

Follow the USB (USB VBUS Detect Voltage Divider / Clamp Circuit) VBUS Design Guidelines section of the device-specific data sheet to scale the external USB VBUS voltage (supply near the USB interface connector) and connecting to USBn_VBUS [n = 0, 1] pins.

Connecting the scaled VBUS (VBUS supply input including Voltage Scaling Resistor Divider / Clamp) input is recommended when the USB interface is configured for device mode. Connection of scaled VBUS (VBUS supply input including Voltage Scaling Resistor Divider / Clamp) is optional when the USB interface is configured for host mode.

Connecting 3.3V or a permanent on-board supply equivalent to the scaled VBUS input, is not recommended or allowed. The USB VBUS input needs to be switched. The fail-safe input condition is valid only when the supply is connected through the recommended VBUS voltage divider and zener diode.

A USB power switch with OC (over current) output indication is recommended when the USB interface is configured as host for VBUS output voltage control. The USBn_DRVVBUS [n = 0, 1] (internal pulldown enabled during and after reset) controls the power switch. The recommendation is to connect the OC output to a processor IO (input) to detect VBUS over load.

For information related to USB connections and On-The-Go feature support, see the device-specific TRM.

When both USB0 and USB1 interfaces are not used, see the Pin Connectivity Requirements section of the device-specific data sheet for connecting the supply pins.

When USB0 or USB1 interface is not used, see the Pin Connectivity Requirements section of the device-specific data sheet for connecting the interface signals and supply pins.

The recommendation is to always provision for USB0 DFU boot for early board builds for board bring-up and debug.

For more information on USB2.0 interface, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP: Custom board hardware design – USB2.0 interface

For more information, see the High-speed Serial Interfaces section in the Peripherals chapter of the device-specific TRM.