SBASAE3 December   2025 ADS125H18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Divider and Input Multiplexer
      2. 7.3.2  Input Range
      3. 7.3.3  ADC Reference Voltage
      4. 7.3.4  Power Supplies
        1. 7.3.4.1 AVDD and AVSS
        2. 7.3.4.2 IOVDD
        3. 7.3.4.3 CAPA and CAPD
        4. 7.3.4.4 Power-On Reset (POR)
      5. 7.3.5  Clock Operation
        1. 7.3.5.1 Internal Oscillator
        2. 7.3.5.2 External Clock
      6. 7.3.6  Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Digital Filter Latency
        2. 7.3.7.2 Sinc3 and Sinc4 Filters
        3. 7.3.7.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.7.4 50/60Hz Notch Filters
      8. 7.3.8  FIFO Buffer
        1. 7.3.8.1 FIFO Buffer Read and Write
        2. 7.3.8.2 FIFO Overflow and Underflow
        3. 7.3.8.3 FIFO Depth Indicator
        4. 7.3.8.4 FIFO Enable and Flush
        5. 7.3.8.5 FIFO Thresholds
      9. 7.3.9  Channel Auto-Sequencer
        1. 7.3.9.1 Auto-Sequencer: Basic Operation
        2. 7.3.9.2 Sequencer Modes
          1. 7.3.9.2.1 Single-Shot Mode
          2. 7.3.9.2.2 Single Step Continuous Conversion Mode
          3. 7.3.9.2.3 Single Sequence Mode
          4. 7.3.9.2.4 Continuous Sequence Mode
        3. 7.3.9.3 Configuring the Auto-Sequencer
        4. 7.3.9.4 Starting and Stopping the Sequencer
        5. 7.3.9.5 Auto-Sequencer and DRDY Behavior
      10. 7.3.10 Offset and Gain Calibration
      11. 7.3.11 Digital PGA
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Open Wire Current Source (OWCS)
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
        5. 7.3.15.5 Resistor Divider Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125H18 Status and General Configuration Page
      2. 7.6.2 ADS125H18 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Applications
      1. 8.2.1 2-Terminal V/I PLC Analog Input Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots - Crosstalk
      2. 8.2.2 3-Terminal V/I PLC Analog Input Module
      3. 8.2.3 2 -Terminal V/I PLC Analog Input Module With Solid State Switch
      4. 8.2.4 2-Terminal, single ended V/I PLC Analog Input Module
      5. 8.2.5 2-Terminal, I-Input PLC Analog Input Module
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.1.2 Detailed Design Procedure

The circuit in Figure 8-4 supports a 2-terminal voltage/current measurement for each channel, meaning each pair of screw terminals can be used to measure either a voltage input signal or a current input signal, depending on the state of the switch selecting or deselecting the shunt resistor. For voltage measurement, the switch is open and the burden resistor (shunt) is inactive. For current measurement, the switch is closed and the burden resistor sinks the 4mA to 20mA input current; the ADC measures the voltage drop across the burden resistor to calculate the current.

As shown in Figure 8-4, the input channel configuration for both voltage and current measurement is differential, meaning that the design supports measurement of voltage or current inputs that are at different common-mode voltages. However, the absolute voltage on any input pin must not exceed the values specified in the Specifications section.

The circuit includes TVS (transient voltage suppressor) diodes between both input terminals and ground. The diodes limit the transient voltage into the ADC to protect the ADC from any unwanted over-voltage fast transients. The breakdown voltage for these diodes must be lower than the maximum allowable input voltage of the ADC inputs (±75V). Also, the clamp voltage of the TVS diode must be higher than the largest sustained terminal voltage, because the TVS diodes are not designed to shunt current indefinitely. For example if a maximum permanent input voltage of 30V is expected (miswiring of a 24V module power with tolerance up to 30V), then the clamping voltage must be higher than 30V. For example, the TVS3301 (±37.5V breakdown) is a good choice for this component.

Two back-to-back zener diodes across the shunt terminals divert the current through the burden resistor in case of a sustained overvoltage event. For example, a breakdown voltage in the order of 11V is recommended when using a burden resistor of 250Ω (depending on the power rating of the shunt - if the shunt can handle the power then the protection components are not required, or can be relaxed). In addition, a PTC fuse limits the current through the shunt in the case of a sustained overvoltage event: a PTC fuse is an element which dramatically increasing the electrical resistance during an overcurrent event, effectively limiting current flow, then automatically resetting as the event cools down, allowing normal operation to resume.

In voltage measurement mode, the circuit in Figure 8-4 supports process-level voltage inputs from –10V to +10V. The voltage signal coming from sensor transmitters or other devices connected to the inputs can exhibit common-mode voltage shifts, requiring an absolute input voltage capability of ±15V (versus GND), see Table 8-2. The ADS125H18-V20 meets this absolute input range requirement, see Table 7-3. This +/10V input voltage plus common-mode is measured directly by the ADS125H18 without the need for external attenuation.

Assuming the leakage currents of all protection components (TVS diodes, Zener, PTC) are negligible, the measurement error for the voltage measurement is solely determined by the TUE (total unadjusted error) of the ADS125H18. Based on the Specifications section, the maximum (3σ) TUE of the ADS125H18 is less than the accuracy targets specified in Table 8-2, see Equation 32 and Equation 33.

Equation 32. E r r V 25 ° C = T U E H 18 25 ° C = 0.06 %   F S R   max ⁡       <   0.1 %   F S R
Equation 33. E r r V - 40 ° C   t o   125 ° C = T U E H 18 - 40 ° C   t o   125 ° C = 0.1 3 %   F S R   max ⁡       <   0 . 2 %   F S R

In current measurement mode, the combined resistance from the burden resistor Rburden and switch Rswconverts the input current Iin to a voltage measured by the ADC VADCin:

Equation 34. V A D C i n =     I i n   × R b u r d e n +   R s w  

The value of the burden resistor is selected based on a tradeoff between power (heat dissipation) and dynamic range. For a maximum current of 24mA and a typical resistance Rburden + Rsw = 250Ω, the maximum differential voltage for ADC input AIN1-AIN0 is 250Ω ⁢× 0.024A = 6V which is well within the absolute input voltage range of the ADS125H18.

To estimate the measurement error in current mode, the errors from the burden resistance Rburden as well as the on-resistance of the switch selecting or deselecting the shunt resistor Rswitch need to be taken into account.

The total current measurement error is a combination of errors from the external shunt resistance (including burden and switch resistance) and the ADC voltage measurement (assuming gain of 1), given by Equation 35.

Equation 35. E r r I 1 σ =     E r r R b u r d e n   2   +     E r r R s w   2 +   E r r V 2  

See the Statistics behind error analysis of ADC system video regarding details on how to perform ADC error analysis.

Select a relay or photoMOS with low on-resistance for the resistor selection. Table 8-3 shows two different photoMOS examples. The impact of the resistance variation on the system accuracy is analyzed in more detail below. 1σ variation refers to the "typical" specification from the data sheet, while 3σ refers to the variation resulting in the "maximum" specification on the device data sheet.

Table 8-3 PhotoMOS Specifications
PARAMETER CPC1002N AQY232G3HS
On-resistance (25°C) 0.35Ω 0.07Ω
On-resistance variation (25°C,3σ) 0.2Ω 0.05Ω

On-resistance variation across temperature

(–40°C to +125°C, 1σ)

 0.2Ω 0.1Ω

Assume a typical (1σ) error at room temperature of 0.033% for the 250Ω burden resistor (maximum 0.1% tolerance), as well as a 0.35Ω ± 0.2Ω (3σ) switch resistance (CPC1002N). The scaled switch resistance error is approximately (0.2Ω/3/250Ω) = 0.026% (1σ). Assuming the typical (1σ) voltage measurement error from the ADC is 0.03% (based on the Specifications section), the total resulting current measurement error (from shunt and ADC) at room temperature is (typical 1σ, and maximum 3σ):

Equation 36. E r r I   25 ° C ,   1 σ =   0.033 % 2   +   0.026 % 2 +   0.03 % 2   = 0.052 %   F S R  
Equation 37. E r r I   25 ° C ,   3 σ =   3   ×   E r r I   25 ° C ,   1 σ = 0 . 155 %   F S R

Therefore, the current measurement error is less than the target as specified in Table 8-2:

Equation 38. E r r I   25 ° C ,   3 σ =   0 . 155 %   F S R < 0.2 %   F S R  

This error can be reduced significantly using a single-temperature system calibration, using the gain and offset calibration registers of the ADS125H18, however the error across temperature still remains.

Across temperature, the drift of the resistances (both burden resistor and switch) have to be taken into account as well. Consider the temperature range of –40°C to +125°C (Δdrift = max (125°C-25°C, 25°C-(-40°C)) = 100°C) as specified in Table 8-2. Assuming a typical drift of the burden resistor of 5ppm/°C, the additional error from the burden resistor is 100°C × 5ppm/°C = 0.05%. Assume the switch on-resistance (CPC1002N) varies typically 0.2Ω across the temperature range, so the switch resistance error (1σ) over temperature is approximately 0.2Ω/250Ω = 0.08%.

Assuming the typical (1σ) additional voltage measurement drift error across temperature from the ADC is 0.04%, the additional resulting current measurement error (from shunt and ADC temperature drifts) across the –40°C to +125°C temperature range is (typical 1σ, and maximum 3σ):

Equation 39. E r r I   - 40 ° C   t o + 125 ° C ,   1 σ =   0.05 % 2   +   0.08 % 2 +   0.04 % 2   = 0.10 %   F S R
Equation 40. E r r I   - 40 ° C   t o + 125 ° C ,   3 σ =   3   ×   E r r I   - 40 ° C   t o + 125 ° C ,   1 σ = 0.30 %   F S R

In an uncalibrated system, the temperature drift given in Equation 40 contributes errors in addition to the room temperature error given in Equation 38. Assuming a room-temperature calibration is performed to minimize the errors in Equation 37, the temperature drift error shown in Equation 40 dominates, and the current measurement error is less than the target as specified in Table 8-2:

Equation 41. E r r I   - 40 ° C   t o + 125 ° C ,   3 σ =   0.30 %   F S R <   0.35 %   F S R

As seen in Equation 36 and Equation 39, the on-resistance of the selection switch adds significant error to the 4mA to 20mA current measurement, and in this analysis on-resistance is the largest contributor to the overall temperature drift error (0.08% term in .Equation 39). Keep the switch resistance and variation as low as possible. When selecting the AQY232G3HS instead of the CPC1002N, the errors calculated in Equation 36 and Equation 39 are further reduced as shown in Table 8-4. Alternatively, select a different architecture that eliminates the switch error contribution, such as the circuit shown in the 3-Terminal V/I PLC Analog Input Module section.

Table 8-4 Current Measurement Error Using Two different PhotoMOS and No Switch
CURRENT MEASUREMENT ERROR TARGET SPECIFICATION SELECT SWITCH USED IN DESIGN:
CPC1002N AQY232G3HS NO SWITCH (2)

Room Temperature

25°C, 3σ

±0.2% FSR 0.16% FSR 0.13% FSR 0.13% FSR

Across Temperature (1)

–40°C to +125°C, 3σ

±0.35% FSR 0.30% FSR 0.23% FSR 0.19% FSR
(1) Assuming a room-temperature system calibration is performed

In summary, the circuit meets the design targets for voltage measurement accuracy outlined in the Design Requirements section, ±0.1%FSR at room temperature and ±0.2%FSR across temperature. Assuming a room-temperature system calibration is performed to minimize errors at room temperature, the circuit also meets the design targets for current measurement outlined in the Design Requirements section; ±0.2%FSR at room temperature and ±0.35%FSR across temperature.