SLLSFO8C May   2024  โ€“ November 2025 TCAN2450-Q1 , TCAN2451-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CAN FD Transceiver
        1. 8.3.1.1 Driver and Receiver Function
      2. 8.3.2  VCC1 Regulator
        1. 8.3.2.1 Functional Description of Buck Regulator
          1. 8.3.2.1.1 Fixed Frequency Peak Current Mode Control
          2. 8.3.2.1.2 Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
          3. 8.3.2.1.3 Overcurrent and Short Circuit Protection
          4. 8.3.2.1.4 Soft Start
        2. 8.3.2.2 Buck Regulator Functional Modes
          1. 8.3.2.2.1 Buck Shutdown Mode
          2. 8.3.2.2.2 Buck Active Modes
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  Reset Function (nRST Pin)
      5. 8.3.5  LIMP Function
      6. 8.3.6  High Side Switches
      7. 8.3.7  WAKE and ID Inputs
        1. 8.3.7.1 ID Functionality
      8. 8.3.8  Interrupt Function (nINT Pin)
      9. 8.3.9  SPI Communication
        1. 8.3.9.1 Cyclic Redundancy Check
        2. 8.3.9.2 Chip Select Not (nCS):
        3. 8.3.9.3 SPI Clock Input (SCK):
        4. 8.3.9.4 SPI Data Input (SDI):
        5. 8.3.9.5 SPI Data Output (SDO):
      10. 8.3.10 SW Pin
      11. 8.3.11 GFO Pin
      12. 8.3.12 Wake Functions
        1. 8.3.12.1 CAN Bus Wake Using RXD Request (BWRR) in Sleep Mode
        2. 8.3.12.2 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.3.12.2.1 Static Wake
          2. 8.3.12.2.2 Cyclic Sensing Wake
        3. 8.3.12.3 Cyclic Wake
        4. 8.3.12.4 Selective Wake-up
          1. 8.3.12.4.1 Selective Wake Mode (TCAN2451-Q1)
          2. 8.3.12.4.2 Frame Detection
          3. 8.3.12.4.3 Wake-Up Frame (WUF) Validation
          4. 8.3.12.4.4 WUF ID Validation
          5. 8.3.12.4.5 WUF DLC Validation
          6. 8.3.12.4.6 WUF Data Validation
          7. 8.3.12.4.7 Frame Error Counter
          8. 8.3.12.4.8 CAN FD Frame Tolerance
          9. 8.3.12.4.9 8Mbps Filtering
      13. 8.3.13 Protection Features
        1. 8.3.13.1 Fail-safe Features
          1. 8.3.13.1.1 Sleep Mode Through Sleep Wake Error
        2. 8.3.13.2 Device Reset
        3. 8.3.13.3 Floating Terminals
        4. 8.3.13.4 TXD Dominant Time Out (DTO)
        5. 8.3.13.5 CAN Bus Short Circuit Current Limiting
        6. 8.3.13.6 Thermal Shutdown
        7. 8.3.13.7 Under and Over Voltage Lockout and Unpowered Device
          1. 8.3.13.7.1 Under-Voltage
            1. 8.3.13.7.1.1 VSUP and VHSS Under-voltage
            2. 8.3.13.7.1.2 VCC1 Under-Voltage
            3. 8.3.13.7.1.3 VCC2 Under-voltage
            4. 8.3.13.7.1.4 VCAN Under-voltage
          2. 8.3.13.7.2 VCC1 and VCC2 Over-voltage
          3. 8.3.13.7.3 VCC1 and VCC2 Short Circuit
        8. 8.3.13.8 Watchdog
          1. 8.3.13.8.1 Watchdog Error Counter and Action
          2. 8.3.13.8.2 Watchdog SPI Programming
            1. 8.3.13.8.2.1 Watchdog Configuration Lock Mechanism
              1. 8.3.13.8.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.3.13.8.3 Watchdog Timing
          4. 8.3.13.8.4 Question and Answer Watchdog
            1. 8.3.13.8.4.1 WD Question and Answer Basic Information
            2. 8.3.13.8.4.2 Question and Answer Register and Settings
            3. 8.3.13.8.4.3 WD Question and Answer Value Generation
              1. 8.3.13.8.4.3.1 Answer Comparison
              2. 8.3.13.8.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
              3. 8.3.13.8.4.3.3 Question and Answer WD Example
                1. 8.3.13.8.4.3.3.1 Example Configuration for Desired Behavior
                2. 8.3.13.8.4.3.3.2 Example of performing a question and answer sequence
        9. 8.3.13.9 Bus Fault Detection and Communication
      14. 8.3.14 Customer EEPROM Programming
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
      6. 8.4.6 Sleep Mode
  10. 9 Device Register Tables
    1. 9.1 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 CAN Bus Biasing
      3. 10.1.3 Device Brownout Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 EMC Requirements:
      3. 11.1.3 Conformance Test Requirements:
      4. 11.1.4 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
8.3.2.1.3 Overcurrent and Short Circuit Protection

The buck regulator incorporates both peak and valley inductor current limit to provide protection to the device from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for sustained short circuits. High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. The peak current of high-side switch is limited by a clamped maximum peak current threshold Isc, which is constant. The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on, the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching cycle if its current is above the low-side current limit ILS_LIMIT . The low-side switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below the ILS_LIMIT. Then the low-side switch is turned OFF and the high-side switch is turned on after a dead time. After ILS_LIMIT is achieved, peak and valley current limit controls the max current delivered to the load and it can be calculated as:

Equation 5. ICC1-max=ILS_LIMIT+ISCรท2

If the internal feedback voltage is lower than VCC133SC threshold (VCC133SC for 3.3V VCC1 and VCC15SC for 5V VCC1), short-circuit protection mode is activated and the TCAN245x-Q1enters fail-safe mode. In fail-safe mode, the buck regulator shuts down. Figure 8-36 describes how the TCAN245x-Q1 exits fail-safe mode after a short-circuit fault on VCC1.