SLLSFO8C May   2024  – November 2025 TCAN2450-Q1 , TCAN2451-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CAN FD Transceiver
        1. 8.3.1.1 Driver and Receiver Function
      2. 8.3.2  VCC1 Regulator
        1. 8.3.2.1 Functional Description of Buck Regulator
          1. 8.3.2.1.1 Fixed Frequency Peak Current Mode Control
          2. 8.3.2.1.2 Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
          3. 8.3.2.1.3 Overcurrent and Short Circuit Protection
          4. 8.3.2.1.4 Soft Start
        2. 8.3.2.2 Buck Regulator Functional Modes
          1. 8.3.2.2.1 Buck Shutdown Mode
          2. 8.3.2.2.2 Buck Active Modes
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  Reset Function (nRST Pin)
      5. 8.3.5  LIMP Function
      6. 8.3.6  High Side Switches
      7. 8.3.7  WAKE and ID Inputs
        1. 8.3.7.1 ID Functionality
      8. 8.3.8  Interrupt Function (nINT Pin)
      9. 8.3.9  SPI Communication
        1. 8.3.9.1 Cyclic Redundancy Check
        2. 8.3.9.2 Chip Select Not (nCS):
        3. 8.3.9.3 SPI Clock Input (SCK):
        4. 8.3.9.4 SPI Data Input (SDI):
        5. 8.3.9.5 SPI Data Output (SDO):
      10. 8.3.10 SW Pin
      11. 8.3.11 GFO Pin
      12. 8.3.12 Wake Functions
        1. 8.3.12.1 CAN Bus Wake Using RXD Request (BWRR) in Sleep Mode
        2. 8.3.12.2 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.3.12.2.1 Static Wake
          2. 8.3.12.2.2 Cyclic Sensing Wake
        3. 8.3.12.3 Cyclic Wake
        4. 8.3.12.4 Selective Wake-up
          1. 8.3.12.4.1 Selective Wake Mode (TCAN2451-Q1)
          2. 8.3.12.4.2 Frame Detection
          3. 8.3.12.4.3 Wake-Up Frame (WUF) Validation
          4. 8.3.12.4.4 WUF ID Validation
          5. 8.3.12.4.5 WUF DLC Validation
          6. 8.3.12.4.6 WUF Data Validation
          7. 8.3.12.4.7 Frame Error Counter
          8. 8.3.12.4.8 CAN FD Frame Tolerance
          9. 8.3.12.4.9 8Mbps Filtering
      13. 8.3.13 Protection Features
        1. 8.3.13.1 Fail-safe Features
          1. 8.3.13.1.1 Sleep Mode Through Sleep Wake Error
        2. 8.3.13.2 Device Reset
        3. 8.3.13.3 Floating Terminals
        4. 8.3.13.4 TXD Dominant Time Out (DTO)
        5. 8.3.13.5 CAN Bus Short Circuit Current Limiting
        6. 8.3.13.6 Thermal Shutdown
        7. 8.3.13.7 Under and Over Voltage Lockout and Unpowered Device
          1. 8.3.13.7.1 Under-Voltage
            1. 8.3.13.7.1.1 VSUP and VHSS Under-voltage
            2. 8.3.13.7.1.2 VCC1 Under-Voltage
            3. 8.3.13.7.1.3 VCC2 Under-voltage
            4. 8.3.13.7.1.4 VCAN Under-voltage
          2. 8.3.13.7.2 VCC1 and VCC2 Over-voltage
          3. 8.3.13.7.3 VCC1 and VCC2 Short Circuit
        8. 8.3.13.8 Watchdog
          1. 8.3.13.8.1 Watchdog Error Counter and Action
          2. 8.3.13.8.2 Watchdog SPI Programming
            1. 8.3.13.8.2.1 Watchdog Configuration Lock Mechanism
              1. 8.3.13.8.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.3.13.8.3 Watchdog Timing
          4. 8.3.13.8.4 Question and Answer Watchdog
            1. 8.3.13.8.4.1 WD Question and Answer Basic Information
            2. 8.3.13.8.4.2 Question and Answer Register and Settings
            3. 8.3.13.8.4.3 WD Question and Answer Value Generation
              1. 8.3.13.8.4.3.1 Answer Comparison
              2. 8.3.13.8.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
              3. 8.3.13.8.4.3.3 Question and Answer WD Example
                1. 8.3.13.8.4.3.3.1 Example Configuration for Desired Behavior
                2. 8.3.13.8.4.3.3.2 Example of performing a question and answer sequence
        9. 8.3.13.9 Bus Fault Detection and Communication
      14. 8.3.14 Customer EEPROM Programming
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
      6. 8.4.6 Sleep Mode
  10. 9 Device Register Tables
    1. 9.1 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 CAN Bus Biasing
      3. 10.1.3 Device Brownout Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 EMC Requirements:
      3. 11.1.3 Conformance Test Requirements:
      4. 11.1.4 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.3.14 Customer EEPROM Programming

The TCAN245x-Q1 family uses EEPROM for two purposes. The first is for device trimming and is not accessible. This portion of EEPROM is monitored and loaded upon power and when exiting sleep mode, checking for a valid CRC. If the CRC is not valid, this process is performed a total of eight time. If still not valid, the INT_3 register 8'h53[0] is set to 1b. Meaning the device has an issue that may impact performance and functionality.

The second use of the EEPROM is to allow the user to store the device configuration. The configuration bits saved are provided in each register. To save the configuration to EEPROM, CRC must be enabled for the save function at a minimum. Saving the configuration to EEPROM is accomplished by writing a 1b to register 8'h4E[7], and default code Ah to 8'h4E[3:0] followed by the CRC byte. See Table 8-25 for procedure if the processor does not support CRC. Register 8'h4E[3:0] reads back 0h. Once the configuration bits have been stored to EEPROM, a 0b is read back from 8'h4E[7]. If a power on reset takes place, the configuration of the device is reloaded from EEPROM. Table 8-26 provides the list of registers and the bits saved to EEPROM if used.

Note:

  • The EEPROM is reprogrammable a maximum of 500 times.

  • REV_ID = 20h: Customer EEPROM Programing is not available in SPI two-byte mode. Contact factory for programing two-byte mode as the default option.
Table 8-25 Process for Non-CRC-Capable Processors
Step Description Register Data Second Data Byte (CRC POLY_8_SET = 0b) Second Data Byte (CRC POLY_8_SET = 1b)
1 Configure device See Table 8-26 N/A N/A N/A
2 Set CRC Polynomial
  • 0x2F AutoSar
  • 0X1D SAE J11850
 8'h0B[0]
  • 00h
  • 01h
  • Selected
  • N/A
  • N/A
  • Selected
3 Enable SPI CRC if not enable 8'h0A[0] 01h N/A N/A
4 Save to EERPOM 8'h4E[7:0] 8Ah 36h 0Ch
5 Disable SPI CRC if not supported 8'h0A[0] 00h 5Eh 6Bh

The saved configuration can be forced to check if the saved configuration CRC is valid but using register 8'h4E[6], EEPROM_CRC_CHK, = 1b. This takes approximately 200 μs to complete. If CRC is valid, then no action is taken, If CRC is not valid, the device attempts this action eight times. If still not valid, the device sets an interrupt indicating there is an issue are INT_4 register 8'h5A[1], EEPROM_CRC_INT.

The following are power and reset scenarios and how the EEPROM is used.

  • UVSUP event; no action as registers are not lost
  • Power on reset event; EEPROM is read and registers restored in Init mode
  • Soft reset; EEPROM is read and registers restored and device transitions to standby mode
  • Hard reset; EERPOM is read and registers restored and device transitions to Init mode
  • nRST input; EEPROM is read and register restored and device transitions to restart mode

Table 8-26 EEPROM Saved Registers and Bits
Register Bits Saved

SPI_CONFIG (Address = 09h)

0-3
SBC_CONFIG (Address = Ch) 0-1, 4, 7
VREG_CONFIG1 (Address = Dh) 3, 5, 6-7
SBC_CONFIG1 Register (Address = Eh) 0, 3-5,
WAKE_PIN_CONFIG1 Register (Address = 11h) 0-3
WAKE_PIN_CONFIG2 Register (Address = 12h 0-1, 5-7
WD_CONFIG_1 Register (Address = 13h) 0-7
WD_CONFIG_2 Register (Address = 14h) 0, 5-7
WD_RST_PULSE Register (Address = 16h) 4-7
DEVICE_CONFIG2 (Address = 1Bh)

2
SWE_TIMER (Address = 1Ch) 3-6, 7
nRST_CNTL (Address = 29h) 4, 5
WAKE_PIN_CONFIG3 Register (Address = 2Ah) 4-7
WAKE_PIN_CONFIG4 Register (Address = 2Bh) 0-1, 3-5, 7
HSS_CNTL3 Register (Address = 4Fh) 0
BUCK_CONFIG1 Register (Address = 65h) 0-7
WAKE_ID_PIN_CONFIG1 Register (Address = 79h) 1-3, 5-7
WAKE_ID_PIN_CONFIG2 Register (Address = 7Ah) 1-3, 5-7
WAKE_PIN_CONFIG5 Register (Address = 7Bh) 4-5, 7