Figure 8-3 shows the block diagram for the CAN FD Transceiver.

The CTXD is the input to the CAN FD transmitter from the processor that controls the state of the CAN FD bus. When CTXD is low, the bus output is dominant. When CTXD is high, the bus output is recessive, which is a logic 0. The CTXD input structure is compatible with processors with 3.3V to 5V V_O. CTXD has an internal pull-up resistor to VCC1. The bus is protected from being stuck dominant through a system failure driving CTXD low through the dominant state time-out timer.

CRXD is the output of the CAN FD receiver. When a CAN wake event takes place the CRXD pin is latched low. CRXD also indicates the local wake up (LWU) from the high voltage WAKE pins. The CRXD is a push-pull output buffer and, as such, an external pull-up is not needed. In restart mode, the RXD pins drive high. When VCC1 is > UVCC1 for t_{RSTN_act}, the device automatically transition to standby mode. The CRXD pin pulls low to indicate a wake up request. Program the CRXD pin to toggle low or high with a pulse width of t_TOGGLE, see Figure 8-16 as an example of this feature.

The VCAN pin is the 5V supply input for the CAN FD transceiver. VCAN is monitored for under-voltage events, UVCAN. When VCAN is present and not in a fault state, register 8'h4F[1], VCAN_STATUS, is set to 1b. For the CAN FD transceiver to be available, VCAN must be present. This pin is also used for EEPROM writing so must be on for this function to happen.

Figure 8-3 CAN Transceiver Block Diagram

Separately program the CAN FD outside of the SBC mode control or tied to the SBC mode control. When tied to the SBC mode control, changing the SBC mode to normal mode automatically changes the transceivers to ON state. All other states are wake capable. When programmed separately than the SBC modes, there are certain states that the transceivers cannot be in for the mode. If a mode change initiates and the transceiver is not in an allowed state, the mode change does not take place, and the MODE_ERR interrupt at 8'h5A[3] is set to 1b. Similarly, if the transceiver state changes to a state not allowed in an SBC mode, the state change does not happen and the MODE_ERR interrupt at 8'h5A[3] is set to 1b. Here are a few specific cases for consideration.

• A transceiver in Normal mode configured for listen, wake capable and off can transition to standby mode, and the state is the same.
• Transitioning to restart mode is wake capable unless the transceiver is programmed off.
• Transitioning from restart mode to standby mode is wake capable unless the transceiver is programmed off.
• When using the SWE timer and the timer times out, the transceivers automatically become wake capable when entering sleep mode or fail-safe mode.

The CAN FD transceiver supports off, on, listen, and wake capable. The state of the transceiver is programmed using register 8'h10[2:0]. On represents normal mode for a stand-alone transceiver. The CAN transceiver defaults to wake capable when entering fail-safe mode, but can be disabled for this mode by using CAN1_FSM_DIS at register 8'h10[3] = 1b.

The V_CAN pin is the 5V supply input for the CAN FD transmitter. V_CAN is monitored for under-voltage events, UVCAN. When V_CAN is present and not in a fault state, register 8'h4F[1], VCAN_STATUS, is set to 1b. For the CAN FD transmitter to be available, VCAN must be present. This pin is also used for EEPROM writing, and VCAN must be present for this function.

When a CAN wake event takes place the CRXD pin is latched low. CRXD also indicates wake up due to WAKEx pins. CRXD pin is a push-pull output and as such an external pull-up is not needed. In restart mode, the CRXD pin is driven high. When VCC1 is > UVCC1 for t_{RSTN_act}, the device automatically transition to standby mode. The CRXD pin is then pulled low to indicate a wake up request. Program the CRXD pin to toggle low or high with a pulse width of t_TOGGLE, see Static Wake as an example of this feature.