SLLSFO8 Data sheet

SLLSFO8C May 2024 – November 2025 TCAN2450-Q1 , TCAN2451-Q1

PRODUCTION DATA

6.9 Switching Characteristics

Over recommended operating conditions with VSUP/VSUPB = 5.5V to 28V unless otherwise noted. All typical values are specified at T_J = 25°C, VSUP/VSUPB = 12V, VCAN = 5V and R_L = 60Ω unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Transmitter and Receiver Characteristics
t_{prop(TxD-busrec)}	Propagation delay time, low-to-high CTXD edge to driver recessive (dominant to recessive)	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, R_CM = open; See Figure 7-4		50	80	ns
t_{prop(TxD-busdom)}	Propagation delay time, high-to-low CTXD edge to driver dominant (recessive to dominant)			50	80	ns
t_sk(p)	Pulse skew (\|t_{prop(TxD-busrec)} – t_{prop(TxD-busdom)}\|)			10	25	ns
t_R	Differential output signal rise time:			30	50	ns
t_F	Differential output signal fall time:			35	55	ns
t_{prop(busrec-RXD)}	Propagation delay time, bus recessive input to CRXD high output (dominant to recessive)	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, R_CM = open, C_RXD = 15pF see Figure 7-5		75	110	ns
t_{prop(busdom-RXD)}	Propagation delay time, bus dominant input to CRXD low output (recessive to dominant)			75	110	ns
t_LOOP	Loop Delay⁽¹⁾	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, C_RXD = 15pF, VCC1 ± 2%, see Section 7			170	ns
CAN FD timing characteristics according to ISO 11898-2:2024 including Signal Improvement Characteristics (SIC); t_bit(TXD) ≥ 125ns. Typical conditions: R_L = 45Ω to 65Ω, C_L = 100pF, C_CRXD = 15pF; See Section 7
t_ΔBit(Bus)	Transmitted bit width variation	Bus recessive bit length variation relative to TXD bit length, Δt_Bit(Bus) = t_Bit(Bus) - t_Bit(TXD)	–10		10	ns
t_ΔBit(RXD)	Received bit width variation	RXD recessive bit length variation relative to TXD bit length, Δt_Bit(RXD) = t_Bit(RXD) - t_Bit(TXD)	–30		20	ns
t_ΔREC	Receiver timing symmetry	RXD recessive bit length variation relative to bus bit length, Δt_REC = t_Bit(RXD) - t_Bit(Bus)	–20		15	ns
t_{REC_START}	Delay time from TXD rising edge to the start of passive recessive phase	See Figure 7-17			530	ns
t_{SIC_START}	Delay time from TXD rising edge to the start of active recessive phase				120	ns
t_{SIC_END}	Delay time from TXD rising edge to the end of active recessive phase		355			ns
SPI Switching Characteristics
f_SCK	SPI clock frequency ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present, if register BYTE_CNT, 09h[3]=0b (single byte mode)			4	MHz
f_SCK	SPI clock frequency ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present, if register BYTE_CNT, 09h[3]=1b (two-byte mode)			2	MHz
t_SCK	SPI clock period ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=0b (single byte mode) See Figure 7-12	250			ns
t_SCK	SPI clock period ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=1b (two-byte mode) See Figure 7-12	500			ns
t_SCKR	SPI clock rise time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-11			40	ns
t_SCKF	SPI clock fall time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12			40	ns
t_SCKH	SPI clock high ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=0b (single byte mode) See Figure 7-12	125			ns
t_SCKH	SPI clock high ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=1b (two-byte mode) See Figure 7-12	250			ns
t_SCKL	SPI clock low ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=0b (single byte mode) See Figure 7-12	125			ns
t_SCKL	SPI clock low ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; if register BYTE_CNT, 09h[3]=1b (two-byte mode) See Figure 7-12	250			ns
t_nCSS	nCS chip select setup time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12	100			ns
t_nCSH	nCS chip select hold time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12	100			ns
t_nCSD	nCS chip select disable time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-11	50			ns
t_SISU	Data in setup time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-11	50			ns
t_SIH	Data in hold time ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-11	50			ns
t_SOV	Data out valid ⁽²⁾	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12			80	ns
t_RSO	SDO rise time ⁽²⁾, C_LOAD <= 20pF	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12			40	ns
t_FSO	SDO fall time ⁽²⁾,C_LOAD <= 20pF	Normal and standby modes and Sleep mode - if VCC1 is present; See Figure 7-12			40	ns

(1) Time span from signal edge on TXD input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.

(2) Specified by design