SLLSFO8 Data sheet

SLLSFO8C May 2024 – November 2025 TCAN2450-Q1 , TCAN2451-Q1

PRODUCTION DATA

6.8 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
Supply
t_PWRUP	Time after VSUP exceedsUVSUP3Rand VCC1> UVCC1. ⁽⁴⁾				5	ms
t_UVFLTR	Under-voltage detection delay time for VCC1 and VCC2 ⁽⁴⁾		25		50	µs
t_UVCC1PR	Under-voltage filter time for VCC1 pre-warning ⁽⁴⁾		2		14	µs
t_UVCANFLTR	Under-voltage filter time for VCAN ⁽⁴⁾		4	10	15	µs
t_OVFLTR-VCC1	Over-voltage detect filter time on VCC1 ⁽⁴⁾		50	60	75	µs
t_OVFLTR-VCC2	Over-voltage detect filter time on VCC2 ⁽⁴⁾		20		40	µs
t_OVFLTRVHSS	Over-voltage detect filter time on VHSS ⁽⁴⁾		4		35	µs
t_VSC-VCC1	Short to ground on VCC1 detection delay time ⁽⁴⁾		75	100	125	µs
t_VSC-VCC2	Short to ground on VCC2 detection delay time ⁽⁴⁾		75	100	125	µs
t_ss-VCC2	VCC2 soft-start time ⁽⁴⁾	V_CC2 from 0V to 4.5V		0.75	1.25	ms
t_REGON	The short circuit filter time for VCC1 at its startup; VCC1 should clear short-circuit threshold before this timer expires. ⁽⁴⁾	See Figure 7-14	3	3.4	3.8	ms
t_VCC2ON	The short circuit filter time for VCC2 at its startup; VCC2 should clear short-circuit threshold before this timer expires. ⁽⁴⁾	See Figure 7-14	3	3.4	3.8	ms
t_REGOFF	Time VCC1 is off in fail-safe mode before accepting wake events and checking for fault conditions ⁽⁴⁾	Time VCC1 is off in fail-safe mode before accepting wake events and checking for fault conditions	250	300	350	ms
Buck Regulator
t_ON-MIN	Minimum switch on-time ⁽⁴⁾	I_CC1 = 1A		70		ns
t_OFF-MIN	Minimum switch off-time ⁽⁴⁾	I_CC1 = 1A		125		ns
t_ON-max	Maximum switch on-time ⁽⁴⁾			7.5		µs
D_MAX	Maximum switch duty cycle ⁽⁴⁾			98		%
t_ss-VCC1	VCC1 soft-start time	V_CC1 from 0V to 90% of V_CC1		1.8	2.1	ms
f_SW	Switching Frequency, register setting 1 ⁽⁴⁾	BUCK_FSW Register field 65h[5:4] = 00b	1.62	1.8	2.1	MHz
f_SW	Switching Frequency, register setting 2 ⁽⁴⁾	BUCK_FSW Register field 65h[5:4] = 01b	1.8	2.0	2.3	MHz
f_SW	Switching Frequency, register setting 3, default setting ⁽⁴⁾	BUCK_FSW Register field 65h[5:4] = 10b	1.98	2.2	2.42	MHz
f_SW	Switching Frequency, register setting 4 ⁽⁴⁾	BUCK_FSW Register field 65h[5:4] = 11b	2.1	2.4	2.7	MHz
f_SS-MOD	Spread Spectrum Modulation Frequency, Setting 1 ⁽⁴⁾	SS_MOD_FREQ Register field 65h[7:6]=00b		0		%
f_SS-MOD	Spread Spectrum Modulation Frequency, Setting 2 ⁽⁴⁾	SS_MOD_FREQ Register field 65h[7:6]=01b ⁽⁶⁾		4		%
f_SS-MOD	Spread Spectrum Modulation Frequency, Setting 3 ⁽⁴⁾	SS_MOD_FREQ Register field 65h[7:6]=10b ⁽⁶⁾		8		%
Mode Change
t_{MODE_STBY_NOM_CTRX}	CAN transceiver state change time based upon SPI write from off or wake capable to on or listen state where CRXD mirror CAN bus ⁽⁴⁾	CAN transceiver state change time based upon SPI write from off or wake capable to on or listen state where CRXD mirrors CAN bus			20	µs
t_{MODE_NOM_SLP}	Time from SPI sleep command where CAN transceiver is off and CRXD doesn't reflect the bus ⁽⁴⁾	See Figure 7-15			5	µs
t_{MODE_NOM_STBY}	SPI write to go to standby from normal mode ⁽⁴⁾	See Figure 7-16			5	µs
Device Timing
t_{RSTN_act}	Time required for VCC1 ≥ UVCC1 to leave Restart mode ⁽⁴⁾	reg 29h[5] = 0b (default); See Figure 7-13, Figure 7-14, Figure 8-16 and Figure 10-3 as examples	1.5	2	2.5	ms
t_{RSTN_act}	Time required for VCC1 ≥ UVCC1 to leave Restart mode ⁽⁴⁾	reg 29h[5] = 1b; See Figure 7-13, Figure 7-14, Figure 8-16 and Figure 10-3 as examples	10	15	20	ms
t_NRSTIN	Input pulse required on the nRST pin to recognize a device reset ⁽⁴⁾	See Figure 8-59.	75	100	125	µs
t_RSTTO	Restart timer timeout. Time required after UVCC1 event before the device enters fail-safe mode (if enabled) or Sleep mode (if fail-safe mode disabled) ⁽⁴⁾		120	150	180	ms
t_{NRST_TOG}	nRST output pulse width ⁽⁴⁾	reg 29h[5] = 0, see Figure 8-59	1.5	2	2.5	ms
t_{NRST_TOG}	nRST output pulse width ⁽⁴⁾	reg 29h[5] = 1, see Figure 8-59	10	15	20	ms
t_{WK_TIMEOUT}	Bus wake-up timeout value⁽⁴⁾	See Figure 8-16	0.8		2	ms
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake up request	See Figure 8-16	0.5		0.95	µs
t_{WK_WIDTH_MIN}⁽²⁾ ⁽³⁾ ⁽⁵⁾	Minimum WAKE Pin pulse width ⁽⁴⁾	WAKE_WIDTH_INVALID = 00b; See Figure 8-20 and Figure 8-21	10			ms
		Minimum WAKE Pin pulse width WAKE_WIDTH_INVALID = 01b; See Figure 8-20 and Figure 8-21	20			ms
		Minimum WAKE Pin pulse width WAKE_WIDTH_INVALID = 10b; See Figure 8-20 and Figure 8-21	40			ms
		Minimum WAKE Pin pulse width WAKE_WIDTH_INVALID = 11b; See Figure 8-20 and Figure 8-21	80			ms
t_{WK_WIDTH_INVALID}⁽²⁾ ⁽³⁾ ⁽⁵⁾	Maximum WAKE Pin pulse width that is considered invalid ⁽⁴⁾	WAKE_WIDTH_INVALID = 00b; See Figure 8-20 and Figure 8-21			5	ms
		Maximum WAKE Pin pulse width that is considered invalid WAKE_WIDTH_INVALID = 01b; See Figure 8-20 and Figure 8-21			10	ms
		Maximum WAKE Pin pulse width that is considered invalid WAKE_WIDTH_INVALID = 10b; See Figure 8-20 and Figure 8-21			20	ms
		Maximum WAKE Pin pulse width that is considered invalid WAKE_WIDTH_INVALID = 11b; See Figure 8-20 and Figure 8-21			40	ms
t_{WK_WIDTH_MAX}⁽²⁾	Maximum WAKE Pin pulse window ⁽⁴⁾	WAKE_WIDTH_MAX = 00b; See Figure 8-20	750		950	ms
		Maximum WAKE Pin pulse window WAKE_WIDTH_MAX = 01b; See Figure 8-20	1000		1250	ms
		Maximum WAKE Pin pulse window WAKE_WIDTH_MAX = 10b; See Figure 8-20	1500		1875	ms
		Maximum WAKE Pin pulse window WAKE_WIDTH_MAX = 11b; See Figure 8-20	2000		2500	ms
t_{WK_CYC}	t_{WK_CYC}⁽⁴⁾	Sampling window for cyclic sensing; Standby or Sleep mode, Register 8'h12[5] = 0b; see Figure 8-23	10	25	35	µs
t_{WK_CYC}	t_{WK_CYC}⁽⁴⁾	Sampling window for cyclic sensing; Standby or Sleep mode, Register 8'h12[5] = 1b; see Figure 8-23	55	70	85	µs
t_{SILENCE_CAN}	t_{SILENCE_CAN}⁽⁴⁾	Timeout for bus inactivity Timer is reset and restarted, when bus changes from dominant to recessive or vice versa.	0.6		1.2	s
t_INACTIVE	t_INACTIVE⁽⁴⁾	SWE timer used for fails-safe and mode inactivity. Can be programmed to different values using register 8'h1C[6:3]	4	5	6	min
t_Bias	t_Bias⁽⁴⁾	Time from the start of a dominant-recessive-dominant sequence. Each phase 6µs until Vsym ≥ 0.1. See Figure 7-10			250	µs
t_SW	SW pin filter time for a state change to be recognized ⁽⁴⁾	SW pin filter time for a state change to be recognized	130			µs
t_INITWD	Initial long window for watchdog ⁽⁴⁾	Initial long window for watchdog, see Figure 8-43	127	150	173	ms
		WD_CONFIG_1 register 8'h13[1:0] = 01b; see Figure 8-42	255	300	345	ms
		WD_CONFIG_1 register 8'h13[1:0] = 10b (default); see Figure 8-42	510	600	690	ms
		WD_CONFIG_1 register 8'h13[1:0] = 11b; see Figure 8-42	850	1000	1150	ms
t_{CTXD_DTO}	t_{CTXD_DTO}⁽⁴⁾	Dominant time out ⁽¹⁾ See , R_L = 60Ω, C_L = open; See Figure 7-7	1		5	ms
t_TOGGLE	t_TOGGLE⁽⁴⁾	CRXD pin toggle timing when programmed after a WUP; See Figure 8-16	5	10	15	µs
t_WD-ACC	Timeout watchdog timing accuracy⁽⁴⁾	Timeout watchdog enabled. Typical values for watchdog timer selected per Table 8-16	–15	tWD	15	%
f_PWM-ACC	HSS1-4 PWM Frequency accuracy ⁽⁴⁾	HSS set to PWM and PWM frequency set to 200Hz or 400Hz per PWMx_FREQ bit	–10		10	%
t_WD-ACC	Window and Q&A watchdog timing accuracy ⁽⁴⁾	Window watchdog or Q&A watchdog enabled. Typical values for watchdog timer selected per Table 8-16	–10	tWD	10	%
t_TMRACC	Timer1, Timer2 period/on-time accuracy OR SWE timer accuracy⁽⁴⁾	Typical value of Timer1 or Timer2 configured per register 8'h25 (TIMER1_CONFIG) or 8'h26 (TIMER2_CONFIG); Typical value of SWE timer configured per 8'h25 (SWE_TIMER_SET)	–15		15	%
F_OSC-16M	16MHz clock frequency		15.36	16	16.64	MHz
F_OSC-1M	1MHz clock frequency		0.94	1.04	1.14	MHz
F_OSC-10k	10kHz clock frequency		8.8	10.4	12	kHz

(1) The CTXD dominant time out (t_{CTXD_DTO}) disables the driver of the transceiver once the CTXD has been dominant longer than t_{CTXD_DTO}, which releases the CAN bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after CTXD has been returned HIGH (recessive). While this protects the CAN bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on CTXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_{CTXD_DTO} minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11÷ t_{CTXD_DTO} = 11 bits ÷ 1.2ms = 9.2kbps.

(2) This parameter is valid only when register 11h[7:6] = 11b

(3) This is the minimum pulse width for a WAKE pin input that device detects as a good pulse. Values between the minimum t_{WK_WIDTH_MIN}and maximum t_{WK_WIDTH_INVALID}is indeterminate and is or is not considered as valid.

(4) Specified by design

(5) This parameter is set based upon the programmed value for t_{WK_WIDTH_INVALID} register 11h[3:2]

(6) Not applicable for devices with REV_ID=20h