SLLSFO8C May   2024  – November 2025 TCAN2450-Q1 , TCAN2451-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CAN FD Transceiver
        1. 8.3.1.1 Driver and Receiver Function
      2. 8.3.2  VCC1 Regulator
        1. 8.3.2.1 Functional Description of Buck Regulator
          1. 8.3.2.1.1 Fixed Frequency Peak Current Mode Control
          2. 8.3.2.1.2 Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
          3. 8.3.2.1.3 Overcurrent and Short Circuit Protection
          4. 8.3.2.1.4 Soft Start
        2. 8.3.2.2 Buck Regulator Functional Modes
          1. 8.3.2.2.1 Buck Shutdown Mode
          2. 8.3.2.2.2 Buck Active Modes
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  Reset Function (nRST Pin)
      5. 8.3.5  LIMP Function
      6. 8.3.6  High Side Switches
      7. 8.3.7  WAKE and ID Inputs
        1. 8.3.7.1 ID Functionality
      8. 8.3.8  Interrupt Function (nINT Pin)
      9. 8.3.9  SPI Communication
        1. 8.3.9.1 Cyclic Redundancy Check
        2. 8.3.9.2 Chip Select Not (nCS):
        3. 8.3.9.3 SPI Clock Input (SCK):
        4. 8.3.9.4 SPI Data Input (SDI):
        5. 8.3.9.5 SPI Data Output (SDO):
      10. 8.3.10 SW Pin
      11. 8.3.11 GFO Pin
      12. 8.3.12 Wake Functions
        1. 8.3.12.1 CAN Bus Wake Using RXD Request (BWRR) in Sleep Mode
        2. 8.3.12.2 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.3.12.2.1 Static Wake
          2. 8.3.12.2.2 Cyclic Sensing Wake
        3. 8.3.12.3 Cyclic Wake
        4. 8.3.12.4 Selective Wake-up
          1. 8.3.12.4.1 Selective Wake Mode (TCAN2451-Q1)
          2. 8.3.12.4.2 Frame Detection
          3. 8.3.12.4.3 Wake-Up Frame (WUF) Validation
          4. 8.3.12.4.4 WUF ID Validation
          5. 8.3.12.4.5 WUF DLC Validation
          6. 8.3.12.4.6 WUF Data Validation
          7. 8.3.12.4.7 Frame Error Counter
          8. 8.3.12.4.8 CAN FD Frame Tolerance
          9. 8.3.12.4.9 8Mbps Filtering
      13. 8.3.13 Protection Features
        1. 8.3.13.1 Fail-safe Features
          1. 8.3.13.1.1 Sleep Mode Through Sleep Wake Error
        2. 8.3.13.2 Device Reset
        3. 8.3.13.3 Floating Terminals
        4. 8.3.13.4 TXD Dominant Time Out (DTO)
        5. 8.3.13.5 CAN Bus Short Circuit Current Limiting
        6. 8.3.13.6 Thermal Shutdown
        7. 8.3.13.7 Under and Over Voltage Lockout and Unpowered Device
          1. 8.3.13.7.1 Under-Voltage
            1. 8.3.13.7.1.1 VSUP and VHSS Under-voltage
            2. 8.3.13.7.1.2 VCC1 Under-Voltage
            3. 8.3.13.7.1.3 VCC2 Under-voltage
            4. 8.3.13.7.1.4 VCAN Under-voltage
          2. 8.3.13.7.2 VCC1 and VCC2 Over-voltage
          3. 8.3.13.7.3 VCC1 and VCC2 Short Circuit
        8. 8.3.13.8 Watchdog
          1. 8.3.13.8.1 Watchdog Error Counter and Action
          2. 8.3.13.8.2 Watchdog SPI Programming
            1. 8.3.13.8.2.1 Watchdog Configuration Lock Mechanism
              1. 8.3.13.8.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.3.13.8.3 Watchdog Timing
          4. 8.3.13.8.4 Question and Answer Watchdog
            1. 8.3.13.8.4.1 WD Question and Answer Basic Information
            2. 8.3.13.8.4.2 Question and Answer Register and Settings
            3. 8.3.13.8.4.3 WD Question and Answer Value Generation
              1. 8.3.13.8.4.3.1 Answer Comparison
              2. 8.3.13.8.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
              3. 8.3.13.8.4.3.3 Question and Answer WD Example
                1. 8.3.13.8.4.3.3.1 Example Configuration for Desired Behavior
                2. 8.3.13.8.4.3.3.2 Example of performing a question and answer sequence
        9. 8.3.13.9 Bus Fault Detection and Communication
      14. 8.3.14 Customer EEPROM Programming
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
      6. 8.4.6 Sleep Mode
  10. 9 Device Register Tables
    1. 9.1 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 CAN Bus Biasing
      3. 10.1.3 Device Brownout Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 EMC Requirements:
      3. 11.1.3 Conformance Test Requirements:
      4. 11.1.4 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
8.3.13.8.4.3.2 Sequence of the 2-bit Watchdog Answer Counter

The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value:

  • WD_ANSW_CNT[1:0] = 11b:
    1. The watchdog calculates the reference Answer-3.
    2. A write access occurs. The MCU writes the Answer-3 byte in WD_QA_ANSWER[7:0].
    3. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_QA_ANSWER[7:0].
    4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 10b and sets the WD_QA_ERR status bit to 1 if the Answer-3 byte is incorrect.
  • WD_ANSW_CNT[1:0] = 10b:
    1. The watchdog calculates the reference Answer-2.
    2. A write access occurs. The MCU writes the Answer-2 byte in WD_QA_ANSWER[7:0].
    3. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_QA_ANSWER[7:0].
    4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 01b and sets the WD_QA_ERR status bit to 1 if the Answer-2 byte is incorrect.
  • WD_ANSW_CNT[1:0] = 01b:
    1. The watchdog calculates the reference Answer-1.
    2. A write access occurs. The MCU writes the Answer-1 byte in WD_QA_ANSWER[7:0].
    3. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_QA_ANSWER[7:0].
    4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 00b and sets the WD_QA_ERR status bit to 1 if the Answer-1 byte is incorrect.
  • WD_ANSW_CNT[1:0] = 00b:
    1. The watchdog calculates the reference Answer-0.
    2. A write access occurs. The MCU writes the Answer-0 byte in WD_QA_ANSWER[7:0].
    3. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_QA_ANSWER[7:0].
    4. The watchdog sets the WD_QA_ERR status bit to 1 if the Answer-0 byte is incorrect.
    5. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 11b.

The MCU needs to clear the bit by writing a '1' to the WD_QA_ERR bit

Table 8-18 Set of WD Questions and Corresponding WD Answers Using Default Setting
QUESTION IN WD_QA_QUESTION REGISTER WD ANSWER BYTES (EACH BYTE TO BE WRITTEN INTO WD_QA_ANSWER REGISTER)
WD_ANSWER_RESP_3 WD_ANSWER_RESP_2 WD_ANSWER_RESP_1 WD_ANSWER_RESP_0
WD_QUESTION WD_ANSW_CNT[1:0] 11b WD_ANSW_CNT[1:0] 10b WD_ANSW_CNT[1:0] 01b WD_ANSW_CNT[1:0] 00b
0x0 FF 0F F0 00
0x1 B0 40 BF 4F
0x2 E9 19 E6 16
0x3 A6 56 A9 59
0x4 75 85 7A 8A
0x5 3A CA 35 C5
0x6 63 93 6C 9C
0x7 2C DC 23 D3
0x8 D2 22 DD 2D
0x9 9D 6D 92 62
0xA C4 34 CB 3B
0xB 8B 7B 84 74
0xC 58 A8 57 A7
0xD 17 E7 18 E8
0xE 4E BE 41 B1
0xF 01 F1 0E FE
TCAN2450-Q1 TCAN2451-Q1 WD Expected Answer Generation Figure 8-46 WD Expected Answer Generation
Table 8-19 Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Multi-Answer Mode
NUMBER OF WD ANSWERS ACTION WD_QA_ERR (in WD_QA_QUESTION Register)(1) COMMENTS
RESPONSE
WINDOW 1		 RESPONSE
WINDOW 2
0 answer 0 answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b No answers
0 answer 4 INCORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received = 4
0 answer 4 CORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received = 4
0 answer 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 CORRECT answer 1 CORRECT answer
2 CORRECT answer 1 CORRECT answer
0 answer 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 CORRECT answer 1 INCORRECT answer
2 CORRECT answer 1 INCORRECT answer
0 answer 4 CORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 CORRECT answer 3 CORRECT answer
2 CORRECT answer 2 CORRECT answer
0 answer 4 INCORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 CORRECT answer 3 INCORRECT answer
2 CORRECT answer 2 INCORRECT answer
0 answer 3 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 INCORRECT answer 2 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b
2 INCORRECT answer 1 CORRECT answer
0 answer 3 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
1 INCORRECT answer 2 INCORRECT answer
2 INCORRECT answer 1 INCORRECT answer
0 answer 4 CORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 INCORRECT answer 3 CORRECT answer 1b
2 INCORRECT answer 2 CORRECT answer
0 answer 4 INCORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4)
1 INCORRECT answer 3 INCORRECT answer
2 INCORRECT answer 2 INCORRECT answer
3 CORRECT answer 0 answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD Question		 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4)
2 CORRECT answer 0 answer 1b
1 CORRECT answer 0 answer
3 CORRECT answer 1 CORRECT answer -New WD cycle starts after the 4th WD answer
-Decrement WD failure counter
-New WD cycle starts with a new WD question		 0b CORRECT SEQUENCE
3 CORRECT answer 1 INCORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received = 4
3 INCORRECT answer 0 answer -New WD cycle starts after the end of RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received < 4
3 INCORRECT answer 1 CORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received = 4
3 INCORRECT answer 1 INCORRECT answer -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b Total Answers Received = 4
4 CORRECT answer Not applicable -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b
3 CORRECT answer + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer
-Increment WD failure counter
-New WD cycle starts with the same WD question		 1b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1
2 CORRECT answer + 2 INCORRECT answer Not applicable
1 CORRECT answer + 3 INCORRECT answer Not applicable
(1) WD_QA_ERR is the logical OR of all QA watchdog errors