SLUUB65B May   2015  – December 2022

 

  1.   Read This First
    1.     Formatting Conventions Used in This Document
    2.     Related Documentation from Texas Instruments
    3.     Trademarks
  2. 1 Introduction
  3. 2 Basic Measurement System
    1. 2.1 Introduction
    2. 2.2 Current and Coulomb Counting
    3. 2.3 Voltage
    4. 2.4 Temperature
  4. 3 Device Power Modes
    1. 3.1 Introduction
      1. 3.1.1 NORMAL Mode
      2. 3.1.2 SLEEP Mode
      3. 3.1.3 FULLSLEEP Mode
      4. 3.1.4 HIBERNATE Mode
    2. 3.2 Power Control
      1. 3.2.1 Reset Functions
      2. 3.2.2 Wake-Up Comparator
      3. 3.2.3 Flash Updates
  5. 4 Device Configuration Registers
    1. 4.1 Introduction
    2. 4.2 Registers Subclass
      1. 4.2.1 Pack Configuration Register
      2. 4.2.2 Pack Configuration B Register
      3. 4.2.3 Pack Configuration C Register
      4. 4.2.4 Pack Configuration D
  6. 5 System Control Function
    1. 5.1 Introduction
    2. 5.2 SHUTDOWN Mode
    3. 5.3 INTERRUPT Mode
    4. 5.4 Low Capacity
    5. 5.5 Battery Level
    6. 5.6 Safety Conditions
      1. 5.6.1 Overtemperature Fault Conditions During Charge/Discharge
      2. 5.6.2 Tab Disconnect Detection
      3. 5.6.3 ISD Faults
    7. 5.7 Battery Trip Point Interrupt Function
  7. 6 Impedance Track Fuel Gauging
    1. 6.1 Introduction
      1. 6.1.1 System Design Parameters
        1. 6.1.1.1 Design Voltage
        2. 6.1.1.2 Cycle Count
        3. 6.1.1.3 Cycle Count Threshold
        4. 6.1.1.4 Design Capacity
        5. 6.1.1.5 Design Energy
        6. 6.1.1.6 State of Health Load I
        7. 6.1.1.7 Design Energy Scale
        8. 6.1.1.8 System Design Parameters DF
    2. 6.2 Gauge FW Operation Modes
      1. 6.2.1 CHARGE Mode
      2. 6.2.2 RELAXATION Mode
      3. 6.2.3 DISCHARGE Mode
    3. 6.3 Current/Power Profiles
      1. 6.3.1 Load Select
      2. 6.3.2 Thermal Rise Factor
      3. 6.3.3 Thermal Time Constant
    4. 6.4 Qmax Update
      1. 6.4.1 Charge Hysteresis Voltage Shift
    5. 6.5 Fast Qmax Update
    6. 6.6 Resistance Update
    7. 6.7 Fast Resistance Scaling
    8. 6.8 StateOfCharge() Smoothing
      1. 6.8.1 SOC Smoothing in Charge/Discharge
      2. 6.8.2 SOC Smoothing in Relaxation
      3. 6.8.3 SOC Smoothing in Overcharge and Overdischarge Conditions
      4. 6.8.4 StateofCharge() Hold at 99%
      5. 6.8.5 StateofCharge() Hold at 1%
    9. 6.9 Additional Impedance Track Gauging Features
      1. 6.9.1 Trace and Downstream Resistance Compensation
      2. 6.9.2 Imax Calculation
      3. 6.9.3 Predict Outside Temp Time
      4. 6.9.4 State Subclass
        1. 6.9.4.1 Qmax Cell 0
        2. 6.9.4.2 Update Status
      5. 6.9.5 OCV Table Class
        1. 6.9.5.1 OCVa Table Subclass
          1. 6.9.5.1.1 Chemistry Identification
      6. 6.9.6 Ra Table Class
        1. 6.9.6.1 Ra0 Subclass
        2. 6.9.6.2 Ra0x Subclass
  8. 7 Charging Features
    1. 7.1 Introduction
    2. 7.2 Charge Suspend
    3. 7.3 Charge Inhibit
    4. 7.4 JEITA Charging Profile
    5. 7.5 Full Charge Termination Detection
    6. 7.6 Pulse Loads
    7. 7.7 Terminate Voltage Valid Time
    8. 7.8 Charge Termination Subclass
      1. 7.8.1 DOD at EOC Delta Temperature
  9. 8 Lifetime Data Logging Features
    1. 8.1 Introduction
    2. 8.2 Lifetime Data Logging Parameters
    3. 8.3 Feature Access
    4. 8.4 Lifetime Data Subclass, Lifetime Resolution Subclass
      1. 8.4.1 Maximum Temperature, Minimum Temperature, Temperature Resolution
      2. 8.4.2 Maximum Pack Voltage, Minimum Pack Voltage, Voltage Resolution
      3. 8.4.3 Maximum Charge Current, Maximum Discharge Current, Current Resolution
    5. 8.5 Lifetime Resolution Subclass
      1. 8.5.1 Lifetime Update Time
    6. 8.6 Lifetime Temp Samples Subclass
      1. 8.6.1 Flash Write Count
  10. 9 Authentication
    1. 9.1 Introduction
    2. 9.2 Key Programming (Data Flash Key)
    3. 9.3 Key Programming (Secure Memory Key)
    4. 9.4 Executing an Authentication Query
    5. 9.5 Codes Subclass
      1. 9.5.1 Sealed to Unsealed
      2. 9.5.2 Unsealed to Full Access
      3. 9.5.3 Authentication Keys
  11. 10Communications
    1. 10.1 HDQ Single-Pin Serial Interface
    2. 10.2 HDQ Host Interruption Feature
      1. 10.2.1 Low Battery Capacity
      2. 10.2.2 Temperature
    3. 10.3 I2C Interface
      1. 10.3.1 I2C Time Out
      2. 10.3.2 I2C Command Waiting Time
      3. 10.3.3 I2C Clock Stretching
  12. 11Manufacturer Information
    1. 11.1 Manufacturer Information Blocks
    2. 11.2 Manufacturer Information Subclass
      1. 11.2.1 Block A and Block B
  13. 12Manufacturer Data
    1. 12.1 Introduction
    2. 12.2 Manufacturer Data Subclass
      1. 12.2.1 Pack Lot Code
      2. 12.2.2 PCB Lot Code
      3. 12.2.3 Firmware Version
      4. 12.2.4 Hardware Revision
      5. 12.2.5 Cell Revision
      6. 12.2.6 Data Flash Configuration Version
  14. 13Integrity Data or Checksum
    1. 13.1 Introduction
    2. 13.2 Data Flash Checksum
  15. 14Calibration
    1. 14.1 Introduction
    2. 14.2 Current Calibration
    3. 14.3 Offset Calibration
      1. 14.3.1 Coulomb Counter Offset/Board Offset
      2. 14.3.2 Internal/External Temperature Offset
      3. 14.3.3 Pack Voltage Offset
      4. 14.3.4 145
    4. 14.4 Current Measurement Noise Filtering
      1. 14.4.1 Filter
      2. 14.4.2 Deadband
      3. 14.4.3 CC Deadband
      4. 14.4.4 150
  16. 15Data Commands
    1. 15.1 Standard Data Commands
      1. 15.1.1  Control(): 0x00 and 0x01
        1. 15.1.1.1  CONTROL_STATUS: 0x0000
        2. 15.1.1.2  DEVICE_TYPE: 0x0001
        3. 15.1.1.3  FW_VERSION: 0x0002
        4. 15.1.1.4  HW_VERSION: 0x0003
        5. 15.1.1.5  RESET_DATA: 0x0005
        6. 15.1.1.6  PREV_MACWRITE: 0x0007
        7. 15.1.1.7  CHEM_ID: 0x0008
        8. 15.1.1.8  BOARD_OFFSET: 0x0009
        9. 15.1.1.9  CC_OFFSET: 0x000A
        10. 15.1.1.10 DF_VERSION: 0x000C
        11. 15.1.1.11 SET_FULLSLEEP: 0x0010
        12. 15.1.1.12 SET_HIBERNATE: 0x0011
        13. 15.1.1.13 CLEAR_HIBERNATE: 0x0012
        14. 15.1.1.14 SET_SHUTDOWN: 0x0013
        15. 15.1.1.15 CLEAR_SHUTDOWN: 0x0014
        16. 15.1.1.16 SET_HDQINTEN: 0x0015
        17. 15.1.1.17 CLEAR_HDQINTEN: 0x0016
        18. 15.1.1.18 STATIC_CHEM_CHKSUM: 0x0017
        19. 15.1.1.19 ALL_DF_CHKSUM: 0x0018
        20. 15.1.1.20 STATIC_DF_CHKSUM: 0x0019
        21. 15.1.1.21 SYNC_SMOOTH: 0x001E
        22. 15.1.1.22 SEALED: 0x0020
        23. 15.1.1.23 IT ENABLE: 0x0021
        24. 15.1.1.24 IMAX_INT_CLEAR: 0x0023
        25. 15.1.1.25 CAL_ENABLE: 0x002D
        26. 15.1.1.26 RESET: 0x0041
        27. 15.1.1.27 EXIT_CAL: 0x0080
        28. 15.1.1.28 ENTER_CAL: 0x0081
        29. 15.1.1.29 OFFSET_CAL: 0x0082
      2. 15.1.2  AtRate(): 0x02 and 0x03
      3. 15.1.3  UnfilteredSOC(): 0x04 and 0x05
      4. 15.1.4  Temperature(): 0x06 and 0x07
      5. 15.1.5  Voltage(): 0x08 and 0x09
      6. 15.1.6  Flags(): 0x0A and 0x0B
      7. 15.1.7  NomAvailableCapacity(): 0x0C and 0x0D
      8. 15.1.8  FullAvailableCapacity(): 0x0E and 0x0F
      9. 15.1.9  RemainingCapacity(): 0x10 and 0x11
      10. 15.1.10 FullChargeCapacity(): 0x12 and 0x13
      11. 15.1.11 AverageCurrent(): 0x14 and 0x15
      12. 15.1.12 TimeToEmpty(): 0x16 and 0x17
      13. 15.1.13 FilteredFCC(): 0x18 and 0x19
      14. 15.1.14 SafetyStatus(): 0x1A and 0x1B
      15. 15.1.15 UnfilteredFCC(): 0x1C and 0x1D
      16. 15.1.16 Imax(): 0x1E and 0x1F
      17. 15.1.17 UnfilteredRM(): 0x20 and 0x21
      18. 15.1.18 FilteredRM(): 0x22 and 0x23
      19. 15.1.19 BTPSOC1Set(): 0x24 and 0x25
      20. 15.1.20 BTPSOC1Clear(): 0x26 and 0x27
      21. 15.1.21 InternalTemperature(): 0x28 and 0x29
      22. 15.1.22 CycleCount(): 0x2A and 0x2B
      23. 15.1.23 StateOfCharge(): 0x2C and 0x2D
      24. 15.1.24 StateOfHealth(): 0x2E and 0x2F
      25. 15.1.25 ChargingVoltage(): 0x30 and 0x31
      26. 15.1.26 ChargingCurrent(): 0x32 and 0x33
      27. 15.1.27 PassedCharge(): 0x34 and 0x35
      28. 15.1.28 DOD0(): 0x36 and 0x37
      29. 15.1.29 SelfDischargeCurrent(): 0x38 and 0x39
    2. 15.2 Extended Data Commands
      1. 15.2.1  PackConfiguration(): 0x3A and 0x3B
      2. 15.2.2  DesignCapacity(): 0x3C and 0x3D
      3. 15.2.3  DataFlashClass(): 0x3E
      4. 15.2.4  DataFlashBlock(): 0x3F
      5. 15.2.5  BlockData(): 0x40 Through 0x5F
      6. 15.2.6  BlockDataCheckSum(): 0x60
      7. 15.2.7  BlockDataControl(): 0x61
      8. 15.2.8  DODatEOC(): 0x62 and 0x63
      9. 15.2.9  Qstart(): 0x64 and 0x65
      10. 15.2.10 FastQmax(): 0x66 and 0x67
      11. 15.2.11 Reserved—0x68 to 0x6C
      12. 15.2.12 Reserved—0x6E and 0x6F
      13. 15.2.13 Reserved—0x70 and 0x71
      14. 15.2.14 Reserved—0x72 and 0x73
      15. 15.2.15 AveragePower(): 0x76 and 0x77
      16. 15.2.16 AN_COUNTER: 0x79
      17. 15.2.17 AN_CURRENT_LSB: 0x7A
      18. 15.2.18 AN_CURRENT_MSB: 0x7B
      19. 15.2.19 AN_VCELL_LSB: 0x7C
      20. 15.2.20 AN_VCELL_MSB: 0x7D
      21. 15.2.21 AN_TEMP_LSB: 0x7E
      22. 15.2.22 AN_TEMP_MSB: 0x7F
  17. 16Data Flash Summary
    1. 16.1 Introduction
    2. 16.2 Data Flash Interface
      1. 16.2.1 Accessing the Data Flash
      2. 16.2.2 Access Modes
      3. 16.2.3 Sealing or Unsealing Data Flash
    3. 16.3 Data Flash Summary Tables
  18. 17Factory Calibration
    1. 17.1  General I2C Command Information
    2. 17.2  Calibration
      1. 17.2.1 Method
      2. 17.2.2 Sequence
    3. 17.3  Enter CALIBRATION Mode
    4. 17.4  Exit CALIBRATION Mode
    5. 17.5  CC Offset
    6. 17.6  Board Offset
    7. 17.7  Obtain Raw Calibration Data
    8. 17.8  Current Calibration
    9. 17.9  Voltage Calibration
    10. 17.10 Temperature Calibration
    11. 17.11 Floating Point Conversion
  19. 18Updating the BQ27542-G1 Firmware
    1. 18.1 Data Flash Stream (.DFFS)/BMS Data Flash Stream (.BQFS) Files
    2. 18.2 Write Command
    3. 18.3 Read and Compare Command
    4. 18.4 Wait Command
    5. 18.5 Firmware Updating Flow
    6. 18.6 Debugging BQFS Reader and Programmer
    7. 18.7 Creating a BQFS and DFFS Containing User-Specific DFI
  20. 19Impedance Track Gauge Configuration
    1. 19.1 Introduction
    2. 19.2 Determining ChemID
    3. 19.3 Learning Cycle
    4. 19.4 Common Problems Seen During the Learning Cycle
    5. 19.5 Test Gauge and Optimize
    6. 19.6 Finalize Golden File
    7. 19.7 Program and Test the PCB
  21. 20Revision History

5.7 Battery Trip Point Interrupt Function

To provide increased flexibility for capacity-based interrupts to the host, the fuel gauge incorporates a Battery Trip Point (BTP) function that allows the system to dynamically update the traditional SOC1 Set Threshold and SOC1 Clear Threshold at runtime using the BTPSOC1Set() and BTPSOC1Clear() standard commands. These thresholds are used to trigger an interrupt on the HDQ pin whenever the set or clear thresholds are crossed following an update to the BTPSOC1Set() and BTPSOC1Clear() values. Configuration of the interrupt polarity and enable/disable of the feature is provided via the Pack Configuration [INTPOL] and Pack Configuration C [BTP_EN] bits, respectively, while initialization values for the interrupt set and clear thresholds are programmed in SOC1 Set Threshold and SOC1 Clear Threshold as normal.

Note:

Enabling of the BTP feature automatically disables all other interrupt sources on the HDQ pin, so care must be taken in configuring the fuel gauge for each particular end application, especially if non-BTP interrupts such as overtemperature, internal short detection, Tab Disconnect Detection, and battery low and high indications are required in the system.

When BTP is enabled, the fuel gauge continuously compares RemainingCapacity() with the values programmed in BTPSOC1Set() and BTPSOC1Clear() to determine whether or not it has crossed below the set or above the clear threshold. Once a threshold is crossed, additional conditions are verified to guard against an unintended interrupt trigger. For the BTP set threshold, the direction of current flow is checked to confirm that a discharge event is occurring. If true, the Flags()[SOC1] bit is set to 1 and an interrupt asserts on the HDQ pin. For the BTP clear threshold, the device again checks the direction of current flow to ensure that a charge event is occurring. Afterwards, an internal variable is examined to determine whether or not a change in the state of Flags()[SOC1] has already occurred due to a prior clear threshold crossing. If true, no change is made and a new interrupt will not fire; however, it is implied that a pre-existing interrupt will still be asserted. If false, the current state of Flags()[SOC1] is flipped to its opposite value and an interrupt subsequently triggered on the HDQ pin. In this way, the correct behavior is guaranteed in cases where the host updates the BTP set and clear thresholds diligently based on HDQ interrupts, but also when there is a failure to update the thresholds. If, at any time, new values are written to either BTPSOC1Set() or BTPSOC1Clear(), then the [SOC1] flag automatically reinitializes to 0 and the HDQ pin de-asserts to its default state. The entire functional flow of the BTP feature is illustrated in Figure 6-1, BTP Algorithm Flow.

GUID-D29EF8BE-982D-47FA-A1FA-B2E646CBBFEE-low.gifFigure 5-1 BTP Algorithm Flow

In normal usage, the BTP thresholds are continuously updated by the host system at predetermined increments, each time reinitializing the Flags()[SOC1] bit to 0 and waiting for the crossing of the next threshold to trigger a new interrupt. If the thresholds are always updated after each interrupt, then it is implied that the crossing of a set or clear threshold always triggers a new interrupt. This is highlighted below in Figure 6-2, BTP Configuration with Multiple Thresholds.

GUID-1D604D5C-CA07-4C23-A357-87BCF0230741-low.gifFigure 5-2 BTP Configuration with Multiple Thresholds

However, it is possible that the host may fail to write new thresholds or experience a significant delay in attempting to do so. In this case, there could be an occurrence where the clear threshold is crossed after an interrupt due to a prior set threshold crossing. Thus, the [SOC1] bit would experience a change but a new interrupt would not be triggered on HDQ. Thus, continued crossings without updates to BTPSOC1Set() or BTPSOC1Clear() will only result in changes to Flags()[SOC1]. Figure 6-3, BTP Configuration with Shared Thresholds, shows the case where identical thresholds are written to BTPSOC1Set() or BTPSOC1Clear(). Figure 6-4, BTP Configuration with Separate Thresholds, shows the alternate case where unique thresholds are written to BTPSOC1Set() or BTPSOC1Clear().

GUID-A38FE581-921F-436B-91F9-4ADC9B6BAB97-low.gifFigure 5-3 BTP Configuration with Shared Thresholds
GUID-530FB0A8-7358-41B9-9C45-3091E1DE1AD7-low.gifFigure 5-4 BTP Configuration with Separate Thresholds