SLUUB65B May 2015 – December 2022
Some algorithm settings are configured via the Pack Configuration C data flash register, as indicated in Table 5-3. This register is programmed and read via the methods described in Section 17.2.1, Accessing the Data Flash. The register is located at subclass = 64, offset = 3.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
FastQmax | FConvTempEn | RlxSmEn | SmoothEn | SleepWkChg | RSVD | RSVD | BTP_EN |
1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 |
0xB9 |
FastQmax = | Fast Qmax feature is enabled. |
FConvTempEn = | Thermal modeling is enabled while in FAST RESISTANCE SCALING mode. Set to 1 to enable. Default of 0 is recommended. |
RlxSmEn = | SOC smoothing is enabled while in battery RELAXATION state. Set to 1 to enable. |
SmoothEn = | Enables SOC smoothing algorithm. True when set. (See Section 7.8, StateOfCharge() Smoothing.) |
SleepWkChg = | Enables compensation for the passed charge missed when waking from SLEEP mode. |
RSVD = | Bits 1 and 2 are reserved. Must be 0. |
BTP_EN = | BTP interrupts are enabled on the HDQ pin. When enabled, all other interrupts are disabled. Set to 1 to enable. |