Enhanced product low power C674x floating-point DSP + Arm9 processor - 345 MHz

Enhanced product low power C674x floating-point DSP + Arm9 processor - 345 MHz



Product details


Arm CPU 1 Arm9 Arm MHz (Max.) 345 Co-processor(s) C674x DSP CPU 32-bit Display type 1 Ethernet MAC 10/100 Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (C) -55 to 125 open-in-new Find other Arm-based processors

Package | Pins | Size

NFBGA (GWT) 361 256 mm² 16 x 16 open-in-new Find other Arm-based processors


  • Highlights
    • Dual Core SoC
      • 345-MHz ARM926EJ-S™ RISC MPU
      • 345-MHz C674x Fixed/Floating-Point VLIW DSP
    • Supports TI’s Basic Secure Boot
    • Enhanced Direct-Memory-Access Controller (EDMA3)
    • Serial ATA (SATA) Controller
    • DDR2/Mobile DDR Memory Controller
    • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface
    • LCD Controller
    • Video Port Interface (VPIF)
    • 10/100 Mb/s Ethernet MAC (EMAC)
    • Programmable Real-Time Unit Subsystem
    • Three Configurable UART Modules
    • USB 1.1 OHCI (Host) With Integrated PHY
    • One Multichannel Audio Serial Port
    • Two Multichannel Buffered Serial Ports
  • Dual Core SoC
    • 345-MHz ARM926EJ-S™ RISC MPU
    • 345-MHz C674x Fixed/Floating-Point VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 16K-Byte Data Cache
    • 8K-Byte RAM (Vector Table)
    • 64K-Byte ROM
  • C674x™ Instruction Set Features
    • Superset of the C67x+™ and C64x+™ ISAs
    • Up to 3648/2746 C674x MIPS/MFLOPS
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two Level Cache Memory Architecture
    • 32K-Byte L1P Program RAM/Cache
    • 32K-Byte L1D Data RAM/Cache
    • 256K-Byte L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct-Memory-Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Non-Aligned Support
    • 64 General-Purpose Registers (32 Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit)
        and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP
        Additions Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP)
        Reciprocal Approximation (RCPxP) and Square-Root Reciprocal
        Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point
        Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed Point Multiply Supports Two 32 × 32-Bit Multiplies,
        Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit
        Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 128K-Byte RAM Shared Memory
  • 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-/16-Bit-Wide Data)
      • NAND (8-/16-Bit-Wide Data)
      • 16-Bit SDRAM With 128 MB Address Space
    • DDR2/Mobile DDR Memory Controller
      • 16-Bit DDR2 SDRAM With 512 MB Address Space or
      • 16-Bit mDDR SDRAM With 256 MB Address Space
    • Three Configurable 16550 type UART Modules:
      • With Modem Control Signals
      • 16-byte FIFO
      • 16x or 13x Oversampling Option
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects
    • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with
      Secure Data I/O (SDIO) Interfaces
    • Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
    • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus
      For High Bandwidth
    • Programmable Real-Time Unit Subsystem (PRUSS)
      • Two Independent Programmable Realtime Unit (PRU) Cores
        • 32-Bit Load/Store RISC architecture
        • 4K Byte instruction RAM per core
        • 512 Bytes data RAM per core
        • PRU Subsystem (PRUSS) can be disabled via software to save power
        • Register 30 of each PRU is exported from the subsystem in addition to the
          normal R31 output of the PRU cores.
      • Standard power management mechanism
        • Clock gating
        • Entire subsystem under a single PSC clock gating domain
      • Dedicated interrupt controller
      • Dedicated switched central resource
    • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
    • USB 2.0 OTG Port With Integrated PHY (USB0)
      • USB 2.0 High-/Full-Speed Client
      • USB 2.0 High-/Full-/Low-Speed Host
      • End Point 0 (Control)
      • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
    • One Multichannel Audio Serial Port:
      • Two Clock Zones and 16 Serial Data Pins
      • Supports TDM, I2S, and Similar Formats
      • DIT-Capable
      • FIFO buffers for Transmit and Receive
    • Two Multichannel Buffered Serial Ports:
      • Supports TDM, I2S, and Similar Formats
      • AC97 Audio Codec Interface
      • Telecom Interfaces (ST-Bus, H100)
      • 128-channel TDM
      • FIFO buffers for Transmit and Receive
    • 10/100 Mb/s Ethernet MAC (EMAC):
      • IEEE 802.3 Compliant
      • MII Media Independent Interface
      • RMII Reduced Media Independent Interface
      • Management Data I/O (MDIO) Module
    • Video Port Interface (VPIF):
      • Two 8-bit SD (BT.656), Single 16-bit or Single Raw (8-/10-/12-bit)
        Video Capture Channels
      • Two 8-bit SD (BT.656), Single 16-bit Video Display Channels
    • Universal Parallel Port (uPP):
      • High-Speed Parallel Interface to FPGAs and Data Converters
      • Data Width on Each of Two Channels is 8- to 16-bit Inclusive
      • Single Data Rate or Dual Data Rate Transfers
      • Supports Multiple Interfaces with START, ENABLE and WAIT Controls
    • Serial ATA (SATA) Controller:
      • Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
      • Supports all SATA Power Management Features
      • Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
      • Supports Port Multiplier and Command-Based Switching
    • Real-Time Clock With 32 KHz Oscillator(1) and Separate Power Rail
    • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
    • One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers)
    • Two Enhanced Pulse Width Modulators (eHRPWM):
      • Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
      • 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
      • Dead-Band Generation
      • PWM Chopping by High-Frequency Carrier
      • Trip Zone Input
    • Three 32-Bit Enhanced Capture Modules (eCAP):
      • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs
      • Single Shot Capture of up to Four Event Time-Stamps
    • 361-Ball SnPb Plastic Ball Grid Array (PBGA) [GWT Suffix], 0.80-mm Ball Pitch
    • Available in Military (-55°C to 125°C) Temperature Range

    Supports Defense, Aerospace, and Medical Applications

    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Extended (–55°C/125°C) Temperature Range
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

    (1) Crystal oscillator cannot be operated beyond 105°C.

open-in-new Find other Arm-based processors


The OMAPL138B C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects the users’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the TMS320C674x/OMAP-L1x Processor Security User’s Guide (SPRUGQ9).

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters.

A Video Port Interface (VPIF) is included providing a flexible video input/output port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

open-in-new Find other Arm-based processors

Technical documentation

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Type Title Date
* Data sheet OMAPL138B-EP C6000 DSP+ARM® Processor datasheet (Rev. C) Apr. 12, 2013
* Errata OMAP-L138 C6000 DSP+ARM Processor (Revs 2.3, 2.1, 2.0, 1.1, & 1.0) Errata (Rev. M) Mar. 21, 2014
* VID OMAPL138B-EP VID V6212605 Jun. 21, 2016
* Radiation & reliability report OMAPL138BGWTMEP Reliability Report Sep. 05, 2013
* Radiation & reliability report OMAPL138BGWTA3R Reliability Report Feb. 06, 2012
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
Application note Processor SDK RTOS Audio Benchmark Starter Kit Apr. 12, 2017
User guide OMAP-L138 C6000 DSP+ARM Processor Technical Reference Manual (Rev. C) Aug. 11, 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug. 13, 2015
Application note Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
Application note nfBGA Packaging (Rev. C) May 17, 0201

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)


The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)


The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)


The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

DSP Math Library for Floating Point Devices
MATHLIB — The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
  • Types of functions included:
    • Trigonometric and hyperbolic: Sin, Cos, Tan, Arctan, etc.
    • Power, exponential, and logarithmic
    • Reciprocal
    • Square root
    • Division
  • Natural C Source Code
  • Optimized C code with Intrinsics
  • Hand-coded assembly-optimized routines
  • C-callable routines, which can be inlined and are fully (...)
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
CODECS- Video, Speech - for C66x-based Devices
C66XCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
  • Field-hardened and tested
  • LINUX and WINDOWS installers
  • XDC packaged and validated on a standard EVM in a Codec Engine-based test
  • Both encoder and decoder are available
  • All codecs are eXpressDSP™ compliant and implement one of the XDM 1.x interfaces
  • Performance data specified in each codec Datasheet
Encode (...)

Design tools & simulation

Arm-based MPU, arm-based MCU and DSP third-party search tool
PROCESSORS-3P-SEARCH TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
  • Supports many TI processors including Sitara and Jacinto processors and DSPs
  • Search by type of product, TI devices supported, or country
  • Links and contacts for quick engagement
  • Third-party companies located around the world

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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