The OMAPL137 is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core.
It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.
The OMAPL137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAPL137 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16Kbyte
data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also
has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAPL137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)
is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache.
The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program
and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM
shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) bus interfaces; 3 multichannel audio serial ports (McASP)
with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of
general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed
with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse
width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced
quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory
interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137
and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO)
interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the device to easily control peripheral devices and/or
communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger
interface for visibility into source code execution.