SM320C6472-HIREL

ACTIVE

Product details

DSP 6 C64x+ DSP MHz (Max) 700 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Military Operating temperature range (C) -40 to 100
DSP 6 C64x+ DSP MHz (Max) 700 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Military Operating temperature range (C) -40 to 100
FCBGA (GTZ) 737 576 mm² 24 x 24
  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320C64x+ DSP
    • 500/625/700 MHz
    • Eight 32-Bit Instructions/Cycle
    • 4000 MIPS/MMACS (16-Bits) at 500 MHz
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
    • L1/L2 Memory Architecture:
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache
        [Direct Mapped, Flexible Allocation]
      • 256K-Bit (32K-Byte) L1D RAM/Cache
        [2-Way Set-Associative, Flexible Allocation]
      • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache
        [4-Way Set-Associative, Flexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
    • Time Stamp Counter
    • One 64-Bit General-Purpose/Watchdog Timer
  • Shared Peripherals and Interfaces
    • EDMA Controller (64 Independent Channels)
    • Shared Memory Architecture
      • Shared L2 Memory Controller
      • 768K-Byte of RAM
      • Boot ROM
    • Three Telecom Serial Interface Ports (TSIPs)
      • Each TSIP is 8 Links of 8 Mbps per Direction
    • 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM)
      • 256 M-Byte × 2 Addressable Memory Space
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
      • 1.25-, 2.5-, 3.125-Gbps Link Rates
      • Message Passing, DirectIO Support, Error Management
        Extensions, and Congestion Control
      • IEEE 1149.6 Compliant I/Os
    • UTOPIA
      • UTOPIA Level 2 Slave ATM Controller
      • 8/16-Bit Transmit and Receive Operations up to
        50 MHz per Direction
      • User-Defined Cell Format up to 64 Bytes
    • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
      • Both EMACs are IEEE 802.3 Compliant
      • EMAC0 Supports:
        • MII, RMII, SS-SMII, GMII, and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • EMAC1 Supports:
        • RMII, SS-SMII and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface
    • 16-Bit Host-Port Interface (HPI)
    • One Inter-Integrated Circuit (I2C) Bus
    • Six Shared 64-Bit General-Purpose Timers
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC
  • Third PLL and PLL Controller Dedicated to DDR2 Memory Controller
  • 16 General-Purpose I/O (GPIO) Pins
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 737-Pin Ball Gird Array (BGA) Package (ZTZ/GTZ Suffix),
    0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
  • 1.0-/1.1-, 1.2-V Core Supplies
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [–40°C to 100°C]
  • Only 625-MHz Device Offered in GTZ Package

  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320C64x+ DSP
    • 500/625/700 MHz
    • Eight 32-Bit Instructions/Cycle
    • 4000 MIPS/MMACS (16-Bits) at 500 MHz
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
    • L1/L2 Memory Architecture:
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache
        [Direct Mapped, Flexible Allocation]
      • 256K-Bit (32K-Byte) L1D RAM/Cache
        [2-Way Set-Associative, Flexible Allocation]
      • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache
        [4-Way Set-Associative, Flexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
    • Time Stamp Counter
    • One 64-Bit General-Purpose/Watchdog Timer
  • Shared Peripherals and Interfaces
    • EDMA Controller (64 Independent Channels)
    • Shared Memory Architecture
      • Shared L2 Memory Controller
      • 768K-Byte of RAM
      • Boot ROM
    • Three Telecom Serial Interface Ports (TSIPs)
      • Each TSIP is 8 Links of 8 Mbps per Direction
    • 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM)
      • 256 M-Byte × 2 Addressable Memory Space
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
      • 1.25-, 2.5-, 3.125-Gbps Link Rates
      • Message Passing, DirectIO Support, Error Management
        Extensions, and Congestion Control
      • IEEE 1149.6 Compliant I/Os
    • UTOPIA
      • UTOPIA Level 2 Slave ATM Controller
      • 8/16-Bit Transmit and Receive Operations up to
        50 MHz per Direction
      • User-Defined Cell Format up to 64 Bytes
    • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
      • Both EMACs are IEEE 802.3 Compliant
      • EMAC0 Supports:
        • MII, RMII, SS-SMII, GMII, and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • EMAC1 Supports:
        • RMII, SS-SMII and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface
    • 16-Bit Host-Port Interface (HPI)
    • One Inter-Integrated Circuit (I2C) Bus
    • Six Shared 64-Bit General-Purpose Timers
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC
  • Third PLL and PLL Controller Dedicated to DDR2 Memory Controller
  • 16 General-Purpose I/O (GPIO) Pins
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 737-Pin Ball Gird Array (BGA) Package (ZTZ/GTZ Suffix),
    0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
  • 1.0-/1.1-, 1.2-V Core Supplies
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [–40°C to 100°C]
  • Only 625-MHz Device Offered in GTZ Package

The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind. A common key requirement of these applications is the availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can eliminate the need for external memory, thereby reducing system power dissipation and system cost and optimizing board density.

The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high performance with the lowest power dissipation per port. The TMS320C6472 device includes three different speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a 16-bit multiplexed host-port interface (HPI16).

The C6472 device has a complete set of development tools which includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind. A common key requirement of these applications is the availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can eliminate the need for external memory, thereby reducing system power dissipation and system cost and optimizing board density.

The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high performance with the lowest power dissipation per port. The TMS320C6472 device includes three different speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a 16-bit multiplexed host-port interface (HPI16).

The C6472 device has a complete set of development tools which includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet Fixed-Point Digital Signal Processor. datasheet (Rev. B) 07 Oct 2010
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Products
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Digital signal processors (DSPs)
DM505 SoC for vision analytics 15mm package SM320C6201-EP Enhanced product C6201 fixed point DSP SM320C6415 Military grade C64x fixed point DSP SM320C6415-EP Enhanced product C6415 fixed point DSP SM320C6424-EP Enhanced product C6424 fixed point DSP SM320C6455-EP Enhanced product C6455 fixed point DSP SM320C6472-HIREL High reliability product 6 Core C6472 fixed point DSP SM320C6678-HIREL High reliability product high performance 8-core C6678 fixed and floating-point DSP SM320C6701 Single core C67x floating-point DSP for military applications - up to 167MHz SM320C6701-EP Enhanced product C6701 floating-point DSP SM320C6711D-EP Enhanced product C6711D floating-point DSP SM320C6712D-EP Enhanced product C6712D DSP SM320C6713B-EP Enhanced product C6713 floating-point DSP SM320C6727B Military grade C6727B floating-point DSP SM320C6727B-EP Enhanced product C6727 floating-point DSP SM320DM642-HIREL High reliability product digital media DM642 DSP SM32C6416T-EP Enhanced product C6416T fixed point DSP SMJ320C6201B Fixed Point Digital Signal Processor, Military SMJ320C6203 Military grade C62x fixed point DSP - ceramic package SMJ320C6415 Military grade C64x fixed point DSP - ceramic package SMJ320C6701 Military grade C67x floating-point DSP - ceramic package SMJ320C6701-SP Space grade C6701 floating-point DSP - rad-tolerant class V with ceramic package SMV320C6727B-SP Space grade C6727B floating-point DSP - rad-tolerant class V with ceramic package TMS320C5517 Low power C55x fixed point DSP- up to 200MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320C5532 Low power C55x fixed point DSP- up to 100MHz TMS320C5533 Low power C55x fixed point DSP- up to 100MHz, USB TMS320C5534 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface TMS320C5535 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320C6201 Fixed-Point Digital Signal Processor TMS320C6202 Fixed-Point Digital Signal Processor TMS320C6202B C62x fixed point DSP- up to 300MHz, 384KB TMS320C6203B C62x fixed point DSP- up to 300MHz, 896KB TMS320C6204 Fixed-Point Digital Signal Processor TMS320C6205 Fixed-Point Digital Signal Processor TMS320C6211B C62x fixed point DSP- up to 167MHz TMS320C6411 C64x fixed point DSP- up to 300MHz, McBSP TMS320C6414 C64x fixed point DSP- up to 720MHz, McBSP TMS320C6415 C64x fixed point DSP- up to 720MHz, McBSP, PCI TMS320C6416 C64x fixed point DSP- up to 720MHz, McBSP, PCI, VCP/TCP TMS320C6421Q C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA, 16-Bit DDR2 TMS320C6424Q C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2 TMS320C6454 C64x+ fixed point DSP- up to 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps Ethernet TMS320C6457 Communications infrastructure digital signal processor TMS320C6701 C67x floating-point DSP- up to 167MHz, McBSP TMS320C6711D C67x floating-point DSP- up to 250MHz, McBSP, 32-Bit EMIFA TMS320C6712D C67x floating-point DSP- up to 150MHz, McBSP, 16-Bit EMIFA TMS320C6720 C67x floating-point DSP - 200MHz, McASP, 16-Bit EMIFA TMS320C6722B C67x floating-point DSP- up to 250MHz, McASP, 16-Bit EMIFA TMS320C6726B C67x floating-point DSP- up to 266MHz, McASP, 16-Bit EMIFA TMS320C6727 C67x floating-point DSP- up to 250MHz, McASP, 32-Bit EMIFA TMS320C6727B C67x floating-point DSP- up to 350MHz, McASP, 32-Bit EMIFA TMS320C6743 Low power C674x floating-point DSP- 375MHz TMS320C6745 Low power C674x floating-point DSP- 456MHz, QFP TMS320C6747 Low power C674x floating-point DSP- 456MHz, PBGA TMS320DM642Q Video/imaging fixed-point digital signal processor TMS320DM6431Q Digital media processor, up to 2400 MIPS, 300 MHz clock rate TMS320DM6435Q Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 1 McBSP TMS320DM6437Q Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 2 McBSP TMS320DM6441 DaVinci Digital Media System-on-Chip TMS320DM6467T Digital Media System-on-Chip TMS320DM647 Digital Media Processor
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Digital signal processors (DSPs)
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Supported products & hardware

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66AK2G12 High performance multicore DSP+Arm - 1x Arm A15 cores, 1x C66x DSP core
Digital signal processors (DSPs)
DM505 SoC for vision analytics 15mm package SM320C6201-EP Enhanced product C6201 fixed point DSP SM320C6415 Military grade C64x fixed point DSP SM320C6415-EP Enhanced product C6415 fixed point DSP SM320C6424-EP Enhanced product C6424 fixed point DSP SM320C6455-EP Enhanced product C6455 fixed point DSP SM320C6472-HIREL High reliability product 6 Core C6472 fixed point DSP SM320C6678-HIREL High reliability product high performance 8-core C6678 fixed and floating-point DSP SM320C6701 Single core C67x floating-point DSP for military applications - up to 167MHz SM320C6701-EP Enhanced product C6701 floating-point DSP SM320C6711D-EP Enhanced product C6711D floating-point DSP SM320C6712D-EP Enhanced product C6712D DSP SM320C6713B-EP Enhanced product C6713 floating-point DSP SM320C6727B Military grade C6727B floating-point DSP SM320C6727B-EP Enhanced product C6727 floating-point DSP SM320DM642-HIREL High reliability product digital media DM642 DSP SM32C6416T-EP Enhanced product C6416T fixed point DSP SMJ320C6201B Fixed Point Digital Signal Processor, Military SMJ320C6203 Military grade C62x fixed point DSP - ceramic package SMJ320C6415 Military grade C64x fixed point DSP - ceramic package SMJ320C6701 Military grade C67x floating-point DSP - ceramic package SMJ320C6701-SP Space grade C6701 floating-point DSP - rad-tolerant class V with ceramic package SMV320C6727B-SP Space grade C6727B floating-point DSP - rad-tolerant class V with ceramic package TMS320C5517 Low power C55x fixed point DSP- up to 200MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320C5532 Low power C55x fixed point DSP- up to 100MHz TMS320C5533 Low power C55x fixed point DSP- up to 100MHz, USB TMS320C5534 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface TMS320C5535 Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface, FFT HWA, SAR ADC TMS320C6201 Fixed-Point Digital Signal Processor TMS320C6202 Fixed-Point Digital Signal Processor TMS320C6202B C62x fixed point DSP- up to 300MHz, 384KB TMS320C6203B C62x fixed point DSP- up to 300MHz, 896KB TMS320C6204 Fixed-Point Digital Signal Processor TMS320C6205 Fixed-Point Digital Signal Processor TMS320C6211B C62x fixed point DSP- up to 167MHz TMS320C6411 C64x fixed point DSP- up to 300MHz, McBSP TMS320C6414 C64x fixed point DSP- up to 720MHz, McBSP TMS320C6415 C64x fixed point DSP- up to 720MHz, McBSP, PCI TMS320C6416 C64x fixed point DSP- up to 720MHz, McBSP, PCI, VCP/TCP TMS320C6421Q C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA, 16-Bit DDR2 TMS320C6424Q C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2 TMS320C6454 C64x+ fixed point DSP- up to 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps Ethernet TMS320C6457 Communications infrastructure digital signal processor TMS320C6701 C67x floating-point DSP- up to 167MHz, McBSP TMS320C6711D C67x floating-point DSP- up to 250MHz, McBSP, 32-Bit EMIFA TMS320C6712D C67x floating-point DSP- up to 150MHz, McBSP, 16-Bit EMIFA TMS320C6720 C67x floating-point DSP - 200MHz, McASP, 16-Bit EMIFA TMS320C6722B C67x floating-point DSP- up to 250MHz, McASP, 16-Bit EMIFA TMS320C6726B C67x floating-point DSP- up to 266MHz, McASP, 16-Bit EMIFA TMS320C6727 C67x floating-point DSP- up to 250MHz, McASP, 32-Bit EMIFA TMS320C6727B C67x floating-point DSP- up to 350MHz, McASP, 32-Bit EMIFA TMS320C6743 Low power C674x floating-point DSP- 375MHz TMS320C6745 Low power C674x floating-point DSP- 456MHz, QFP TMS320C6747 Low power C674x floating-point DSP- 456MHz, PBGA TMS320DM642Q Video/imaging fixed-point digital signal processor TMS320DM6431Q Digital media processor, up to 2400 MIPS, 300 MHz clock rate TMS320DM6435Q Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 1 McBSP TMS320DM6437Q Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 2 McBSP TMS320DM6441 DaVinci Digital Media System-on-Chip TMS320DM6467T Digital Media System-on-Chip TMS320DM647 Digital Media Processor
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CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

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Products
Automotive mmWave radar sensors
AWR1243 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 Automotive 2nd-generation, 76-GHz to 81-GHz, high-performance SoC for corner and long-range radar AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU
Industrial mmWave radar sensors
IWR1443 Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
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PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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