The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor
(DSP) targeting high-performance computing applications, including high-end industrial, mission-critical,
high-end image and video, communication, media gateways, and remote access servers. This device was
designed with these applications in mind. A common key requirement of these applications is the
availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte
of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can
eliminate the need for external memory, thereby reducing system power dissipation and system cost and
optimizing board density.
The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high
performance with the lowest power dissipation per port. The TMS320C6472 device includes three different
speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance
fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on
the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for
applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI).
The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™
The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like
the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+
megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four
16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be
executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can
occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one
32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.
The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory
system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This
memory can be configured as mapped RAM, cache, or some combination of the two. When configured as
cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative
cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2
memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+
megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a
system component with reset/boot control, interrupt/exception control, a power-down control, and a
free-running 32-bit timer for time stamp.
The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and
Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two
10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the
C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by
both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the
system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM
interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16
general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a
16-bit multiplexed host-port interface (HPI16).
The C6472 device has a complete set of development tools which includes: a C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into
source code execution.