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C6472 DSP HIREL

SM320C6472-HIREL

ACTIVE

Product details

Parameters

DSP 6 C64x+ On-chip L2 cache/RAM 3648 KB Other on-chip memory 768 KB Operating system DSP/BIOS DRAM DDR2, SDRAM Ethernet MAC 10/100/1000 I2C 1 Operating temperature range (C) -40 to 100 Rating HiRel Enhanced Product open-in-new Find other C6000 floating-point DSPs

Package | Pins | Size

FCBGA (GTZ) 737 576 mm² 24 x 24 open-in-new Find other C6000 floating-point DSPs

Features

  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320C64x+ DSP
    • 500/625/700 MHz
    • Eight 32-Bit Instructions/Cycle
    • 4000 MIPS/MMACS (16-Bits) at 500 MHz
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
    • L1/L2 Memory Architecture:
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache
        [Direct Mapped, Flexible Allocation]
      • 256K-Bit (32K-Byte) L1D RAM/Cache
        [2-Way Set-Associative, Flexible Allocation]
      • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache
        [4-Way Set-Associative, Flexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
    • Time Stamp Counter
    • One 64-Bit General-Purpose/Watchdog Timer
  • Shared Peripherals and Interfaces
    • EDMA Controller (64 Independent Channels)
    • Shared Memory Architecture
      • Shared L2 Memory Controller
      • 768K-Byte of RAM
      • Boot ROM
    • Three Telecom Serial Interface Ports (TSIPs)
      • Each TSIP is 8 Links of 8 Mbps per Direction
    • 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM)
      • 256 M-Byte × 2 Addressable Memory Space
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
      • 1.25-, 2.5-, 3.125-Gbps Link Rates
      • Message Passing, DirectIO Support, Error Management
        Extensions, and Congestion Control
      • IEEE 1149.6 Compliant I/Os
    • UTOPIA
      • UTOPIA Level 2 Slave ATM Controller
      • 8/16-Bit Transmit and Receive Operations up to
        50 MHz per Direction
      • User-Defined Cell Format up to 64 Bytes
    • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
      • Both EMACs are IEEE 802.3 Compliant
      • EMAC0 Supports:
        • MII, RMII, SS-SMII, GMII, and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • EMAC1 Supports:
        • RMII, SS-SMII and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface
    • 16-Bit Host-Port Interface (HPI)
    • One Inter-Integrated Circuit (I2C) Bus
    • Six Shared 64-Bit General-Purpose Timers
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC
  • Third PLL and PLL Controller Dedicated to DDR2 Memory Controller
  • 16 General-Purpose I/O (GPIO) Pins
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 737-Pin Ball Gird Array (BGA) Package (ZTZ/GTZ Suffix),
    0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
  • 1.0-/1.1-, 1.2-V Core Supplies
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [–40°C to 100°C]
  • Only 625-MHz Device Offered in GTZ Package

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Description

The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind. A common key requirement of these applications is the availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can eliminate the need for external memory, thereby reducing system power dissipation and system cost and optimizing board density.

The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high performance with the lowest power dissipation per port. The TMS320C6472 device includes three different speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a 16-bit multiplexed host-port interface (HPI16).

The C6472 device has a complete set of development tools which includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Fixed-Point Digital Signal Processor. datasheet (Rev. B) Oct. 07, 2010
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
Features
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors
CCSTUDIO-KEYSTONE

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

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Package Pins Download
FCBGA (GTZ) 737 View options

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