SMJ320C6701-SP

ACTIVE

Rad-Tolerant Class V, Floating Point Digital Signal Processor

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Rad-Tolerant Class V, Floating Point Digital Signal Processor

SMJ320C6701-SP

ACTIVE

Product details

Parameters

DSP 1 C67x On-chip L2 cache/RAM 64 KB Total on-chip memory (KB) 128 Operating systems DSP/BIOS Serial I/O McBSP SPI 2 Operating temperature range (C) -55 to 125 Rating Space open-in-new Find other C6000 floating-point DSPs

Package | Pins | Size

CFCBGA (GLP) 429 FCLGA (ZMB) 429 729 mm² 27 x 27 open-in-new Find other C6000 floating-point DSPs

Features

  • Rad-Tolerant: 100-kRad (Si) TID
  • SEL Immune at 89MeV-cm2/mg LET Ions
  • QML-V Qualified, SMD 5962-98661
  • Highest-Performance Floating-Point Digital
    Signal Processor (DSP) SMJ320C6701
    • 7-ns Instruction Cycle Time
    • 140-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Up to One GFLOPS Performance
    • Pin Compatible With ’C6201 Fixed-Point DSP
  • SMJ: QML Processing to MIL-PRF-38535
  • SM: Standard Processing
  • Operating Temperature Ranges
    • –55°C to 115°C
    • –55°C to 125°C
  • VelociTI Advanced Very Long Instruction
    Word (VLIW) ’C67x CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating and Fixed Point)
      • Two ALUs (Fixed Point)
      • Two Multipliers (Floating and Fixed Point)
    • Load-Store Architecture With 32
      32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision
      Instructions
    • Hardware Support for IEEE Double-Precision
      Instructions
    • Byte Addressable (8-/16-/32-Bit Data)
    • 32-Bit Address Range
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache
      (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data
      (64K Bytes)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
  • Four-Channel Bootloading
    Direct Memory Access (DMA) Controller
    With Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST Bus Switching Compatible
    • Up to 256 Channels Each
    • AC97 Compatible
    • Serial Peripheral Interface (SPI)
      Compatible (Motorola)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE Std 1149.1 (JTAG(1))
    Boundary Scan Compatible
  • 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and
    Ceramic Land Grid Array (CLGA/ZMB) Package Types
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.9 V Internal
  • Engineering Evaluation (/EM) Samples are Available(2)

(1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan Architecture
(2) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.

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Description

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technical documentation

= Featured
No results found. Please clear your search and try again. View all 9
Type Title Date
* Datasheet Rad-Tolerant Class-V Floating-Point Digital Signal Processor datasheet (Rev. F) Sep. 26, 2013
Radiation & Reliability reports Heavy Ion Orbital Environment Single-Event Effects Estimations May 18, 2020
Radiation & Reliability reports Single-Event Effects Confidence Interval Calculations Jan. 14, 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing Jun. 17, 2019
SMD SMJ320C6701-SP SMD 5962-98661 Jul. 08, 2016
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
More literature QML Class V Product Portfolio Sep. 02, 2004
More literature SMJ320C6701/5962-9866101QXA (Rev. M) May 03, 2002
More literature Military C6000 DSPs (Rev. A) May 08, 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$995.00
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$1,495.00
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
Features
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)

Design tools & simulation

SIMULATION MODELS Download
SCTM052A.ZIP (4 KB) - BSDL Model
SIMULATION MODELS Download
SGUM001.ZIP (8 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
CFCBGA (GLP) 429 View options
FCLGA (ZMB) 429 View options

Ordering & quality

Support & training

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