C67x floating-point DSP- up to 150MHz, McBSP, 16-Bit EMIFA

TMS320C6712D

ACTIVE

Product details

DSP 1 C67x DSP MHz (Max) 100, 150 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) 0 to 90
DSP 1 C67x DSP MHz (Max) 100, 150 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) 0 to 90
BGA (GDP) 272 729 mm² 27 x 27 BGA (ZDP) 272 729 mm² 27 x 27
  • Low-Price/High-Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6712D
    • Eight 32-Bit Instructions/Cycle
    • 150-MHz Clock Rate
    • 6.7-ns Instruction Cycle Time
    • 900 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: 8- and 16-Bit ROM Boot
    • Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software-Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/Os, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.

TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6712D shall be referred to as its individual full device part number or abbreviated as C6712D or 12D.

  • Low-Price/High-Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6712D
    • Eight 32-Bit Instructions/Cycle
    • 150-MHz Clock Rate
    • 6.7-ns Instruction Cycle Time
    • 900 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: 8- and 16-Bit ROM Boot
    • Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software-Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/Os, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.

TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6712D shall be referred to as its individual full device part number or abbreviated as C6712D or 12D.

The TMS320C67x™ DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices) are members of the floating-point DSP family in the TMS320C6000. DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6712D device is the lowest-cost DSP in the C6000™ DSP platform. The C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712D can produce two MACs per cycle for a total of 300 MMACS.

The C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712D device also includes a dedicated general-purpose input/output (GPIO) peripheral module.

The C6712D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C67x™ DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices) are members of the floating-point DSP family in the TMS320C6000. DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6712D device is the lowest-cost DSP in the C6000™ DSP platform. The C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712D can produce two MACs per cycle for a total of 300 MMACS.

The C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712D device also includes a dedicated general-purpose input/output (GPIO) peripheral module.

The C6712D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

Technical documentation

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Type Title Date
* Data sheet TMS320C6712D Floating-Point Digital Signal Processor datasheet (Rev. B) 30 Jun 2006
* Errata TMS320C6712/C6712C/C6712D DSPs Silicon Errata (Revs 1.0, 1.1, 1.2, 1.3, 2.0) (Rev. O) 12 Aug 2005
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) 19 May 2021
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 Jul 2009
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 May 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 Apr 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14 Dec 2006
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15 Nov 2006
Application note Migrating from TMS320C6712/C6712C to TMS320C6712D (Rev. F) 11 Nov 2005
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 Mar 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 Jan 2005
User guide TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. C) 02 Aug 2004
User guide TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 08 Jun 2004
Application note TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A) 31 May 2004
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 25 Mar 2004
Application note TMS320C6000 EDMA IO Scheduling and Performance 05 Mar 2004
Application note TMS320C621x/671x EDMA Performance Data 05 Mar 2004
Application note TMS320C621x/TMS320C671x EDMA Architecture 05 Mar 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Driver or library

MATHLIB — DSP Math Library for Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Simulation model

C6712D GDP IBIS Model

SPRM144.ZIP (68 KB) - IBIS Model
Simulation model

C6712D GDP BSDL Model

SPRM215.ZIP (6 KB) - BSDL Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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Ordering & quality

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  • Ongoing reliability monitoring

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