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TMS320C6743

ACTIVE

Low power C674x floating-point DSP- 375MHz

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Data sheet
User guides

TMS320C6743

ACTIVE
Data sheet Order now

Product details

CPU 32-/64-bit Frequency (MHz) 200, 375 Features 1 RTC, 3 enhanced-capture peripherals Operating system TI RTOS Rating Catalog Operating temperature range (°C) -40 to 125
CPU 32-/64-bit Frequency (MHz) 200, 375 Features 1 RTC, 3 enhanced-capture peripherals Operating system TI RTOS Rating Catalog Operating temperature range (°C) -40 to 125
PBGA (ZKB) 256 289 mm² (17 mm × 17 mm) HLQFP (PTP) 176 676 mm² (26 mm × 26 mm)
  • Applications
    • Networking
    • High-Speed Encoding
    • Professional Audio™
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • 3000 MIPS and 2250 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 128KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 3.3-V LVCMOS I/Os
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-Bit-Wide Data)
      • NAND (8-Bit-Wide Data)
    • EMIFB
      • 16-bit SDRAM, up to 128MB
  • Two Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • One Serial Peripheral Interface (SPI) with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Two Multichannel Audio Serial Ports (McASPs):
    • Supports TDM, I2S, and Similar Formats
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Event Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
  • Commercial or Automotive Temperature
  • Applications
    • Networking
    • High-Speed Encoding
    • Professional Audio™
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • 3000 MIPS and 2250 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 128KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 3.3-V LVCMOS I/Os
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-Bit-Wide Data)
      • NAND (8-Bit-Wide Data)
    • EMIFB
      • 16-bit SDRAM, up to 128MB
  • Two Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • One Serial Peripheral Interface (SPI) with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Two Multichannel Audio Serial Ports (McASPs):
    • Supports TDM, I2S, and Similar Formats
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Event Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
  • Commercial or Automotive Temperature

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet TMS320C6743 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. D) PDF | HTML Jun 17, 2014
* User guide OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) Sep 21, 2016
* User guide TMS320C6743 DSP Technical Reference Manual (Rev. D) Sep 21, 2016
* Errata TMS320C6743 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G) Jun 17, 2014
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML May 19, 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun 1, 2020
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML Jun 11, 2019
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx PDF | HTML Apr 25, 2019
Application note TMS320C6747/45/43 Power Consumption Summary Apr 23, 2019
Application note General Hardware Design/BGA PCB Design/BGA PDF | HTML Feb 22, 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples Jan 10, 2019
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug 13, 2015
User guide System Analyzer User's Guide (Rev. F) Nov 18, 2013
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug 21, 2012
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug 21, 2012
Application note Using the TMS320C6747/45/43 Bootloader (Rev. C) Jun 1, 2012
Application note Using the OMAP-L1x7 Bootloader (Rev. G) Jun 1, 2012
Application note Introduction to TMS320C6000 DSP Optimization Oct 6, 2011
User guide TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) Sep 14, 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
User guide TMS320C674x DSP Megamodule Reference Guide (Rev. A) Aug 3, 2010
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) Jul 30, 2010
Application note OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A) Sep 26, 2009
Application note TMS320C6747/45/43 Complementary Products Sep 23, 2009
White paper Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core Jun 24, 2009
Application note TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing Mar 12, 2009
Application note TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing Mar 12, 2009
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist Mar 12, 2009
User guide TMS320C674x DSP Cache User's Guide (Rev. A) Feb 11, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TMDSOSKL137 — OMAP-L137/TMS320C6747 Floating Point Starter Kit

The OMAP-L137/TMS320C6747 Floating-Point Starter Kit, developed jointly with Spectrum Digital Inc., is a low-cost development platform designed to speed the development of high-precision applications based on TI's OMAP-L13x applications processors and TMS320C674x fixed-/floating-point DSPs (...)

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Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. For the majority of devices it is recommended to use the newer, lower cost XDS110 (www.ti.com/tool/TMDSEMU110-U). The XDS200 supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. All XDS (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Supported products & hardware
In stock
Limit:
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Debug probe

LB-3P-TRACE32-DSP — Lauterbach TRACE32 Debug and Trace System for Digital Signal Processors (DSPs)

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

From: Lauterbach GmbH
Supported products & hardware
Software development kit (SDK)

PROCESSOR-SDK-C6747 — Processor SDK for C6747 Processors TI-RTOS Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware
IDE, configuration, compiler or debugger

CCSTUDIO — CCStudio™ IDE

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Supported products & hardware
Driver or library

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Supported products & hardware
Driver or library

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Supported products & hardware
Driver or library

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Supported products & hardware
Driver or library

C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
Supported products & hardware
Driver or library

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Supported products & hardware
Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Supported products & hardware
Driver or library

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Supported products & hardware
Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
From: Adaptive Digital Technologies, Inc.
Supported products & hardware
Simulation model

C6743 PTP BSDL Model (Rev. B)

SPRM385 (5 KB) - BSDL model
Supported products & hardware
Simulation model

C6743 PTP IBIS Model (Rev. B)

SPRM388B.ZIP (109 KB) - IBIS model
Supported products & hardware
Simulation model

C6743 ZKB BSDL Model (Rev. B)

SPRM386 (5 KB) - BSDL model
Supported products & hardware
Simulation model

C6743 ZKB IBIS Model (Rev. B)

SPRM387B.ZIP (176 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
PBGA (ZKB) 256 Ultra Librarian
HLQFP (PTP) 176 Ultra Librarian
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