C62x fixed point DSP- up to 167MHz



Product details


DSP 1 C62x DSP MHz (Max) 150, 167 CPU 32-/64-bit Rating Catalog open-in-new Find other Digital signal processors (DSPs)

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BGA (GFN) 256 729 mm² 27 x 27 open-in-new Find other Digital signal processors (DSPs)


  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Data sheet TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors datasheet (Rev. L) Jun. 09, 2004
* Errata TMS320C6211/TMS320C6211B DSPs Silicon Errata (Revs 1.0, 1.1, 2.1, 2.2, 3.0, 3.1) (Rev. L) May 28, 2004
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) May 19, 2021
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016
Application note Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guide TMS320C62x DSP CPU and Instruction Set Reference Guide (Rev. A) May 20, 2010
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) Jul. 02, 2009
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) Sep. 04, 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) Apr. 11, 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) Dec. 14, 2006
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) Nov. 15, 2006
User guide TMS320C6000 CPU and Instruction Set Reference Guide (Rev. G) Jul. 11, 2006
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) Jan. 01, 2006
Application note Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H) Nov. 11, 2005
Application note Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) Nov. 10, 2005
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) Mar. 01, 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) Jan. 25, 2005
User guide TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) Jun. 08, 2004
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) Apr. 26, 2004
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) Apr. 21, 2004
Application note TMS320C6000 McBSP Initialization (Rev. C) Mar. 08, 2004
Application note TMS320C621x/671x EDMA Performance Data Mar. 05, 2004
Application note TMS320C621x/TMS320C671x EDMA Architecture Mar. 05, 2004
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide Jul. 31, 2003
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) May 05, 2003
Application note Migrating from TMS320C6211 to TMS320C6211B Apr. 28, 2003
Application note Using IBIS Models for Timing Analysis (Rev. A) Apr. 15, 2003
Application note Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x Nov. 23, 2002
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) Jun. 04, 2002
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) Apr. 17, 2002
Application note TMS320C6000 DMA Example Applications (Rev. A) Apr. 10, 2002
Application note TMS320C6000 Board Design for JTAG (Rev. C) Apr. 02, 2002
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) Feb. 13, 2002
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) Oct. 31, 2001
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) Oct. 24, 2001
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) Sep. 30, 2001
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) Sep. 30, 2001
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) Aug. 31, 2001
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) Aug. 31, 2001
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) Aug. 31, 2001
Application note TMS320C6000 System Clock Circuit Example (Rev. A) Aug. 15, 2001
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) Jul. 23, 2001
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) Jul. 10, 2001
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) Jun. 30, 2001
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) Jun. 21, 2001
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) May 21, 2001
Application note ETSI Math Operations in C for the TMS320C62x (Rev. A) Nov. 13, 2000
Application note TMS320C621x/C671x EDMA Queue Management Guidelines Nov. 07, 2000
Application note Optimizing JPEG on the TMS320C6211 2-Level Cache DSP Sep. 13, 2000
Application note Circular Buffering on TMS320C6000 (Rev. A) Sep. 12, 2000
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) Sep. 11, 2000
Application note MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation Feb. 29, 2000
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP Feb. 02, 2000
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point Jan. 31, 2000
Application note G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) Jan. 04, 2000
Application note G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) Jan. 04, 2000
Application note GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) Jan. 04, 2000
Application note IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B) Jan. 04, 2000
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics Dec. 07, 1999
Application note TMS320C6000 McBSP: I2S Interface Sep. 08, 1999
Application note On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x Jul. 29, 1999

Design & development

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Software development

C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)


  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  


  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)

Design tools & simulation

SPRM036B.ZIP (5 KB) - BSDL Model
Arm-based MPU, arm-based MCU and DSP third-party search tool
PROCESSORS-3P-SEARCH TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
  • Supports many TI processors including Sitara and Jacinto processors and DSPs
  • Search by type of product, TI devices supported, or country
  • Links and contacts for quick engagement
  • Third-party companies located around the world

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