Inicio Administración de potencia Controladores LED Controladores para LED en automóviles

TPIC6595

ACTIVO

Registro de desplazamiento de 8 bits con 250 mA/canal

Se encuentra disponible una versión más nueva de este producto

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Misma funcionalidad con diferente configuración de pines que el dispositivo comparado
TLC6C598-Q1 ACTIVO Controlador LED de registro de desplazamiento de 8 bits de la lógica de potencia para automoción Same output channel with smaller footprint and support lower supply voltage

Detalles del producto

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 45 Features Enable/Shutdown, Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 45 Features Enable/Shutdown, Thermal shutdown
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Low rDS(on): 1.3Ω typical
  • Avalanche energy: 75mJ
  • Eight power DMOS transistor outputs of 250mA continuous current
  • 1.5A pulsed current per output
  • Output clamp voltage at 45V
  • Devices can cascade
  • Low power consumption
  • Low rDS(on): 1.3Ω typical
  • Avalanche energy: 75mJ
  • Eight power DMOS transistor outputs of 250mA continuous current
  • 1.5A pulsed current per output
  • Output clamp voltage at 45V
  • Devices can cascade
  • Low power consumption

The TPIC6595 is a monolithic, high-voltage, high-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.

Outputs are low-side, open-drain DMOS transistors with output ratings of 45V and 250mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6595 is characterized for operation over the operating case temperature range of −40°C to 125°C.

The TPIC6595 is a monolithic, high-voltage, high-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.

Outputs are low-side, open-drain DMOS transistors with output ratings of 45V and 250mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6595 is characterized for operation over the operating case temperature range of −40°C to 125°C.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos TPIC6595 Power Logic 8-bit Shift Register datasheet (Rev. C) PDF | HTML 16/03/2025
Nota sobre la aplicación TPIC6595 Power+ Logic(TM) 8-Bit Shift Reg. With Low-Side Power DMOS Switches (Rev. A) 1/07/1993

Diseño y desarrollo

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (DW) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian

Pedidos y calidad

Soporte y capacitación

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