DS90UH927Q-Q1
- Integrated HDCP Cipher Engine with On-Chip Key
Storage - Bidirectional Control Channel Interface with I2C
Compatible Serial Control Bus - Low EMI FPD-Link Video Input
- Supports High Definition (720p) Digital Video
Format - 5-MHz to 85-MHz PCLK Supported
- RGB888 + VS, HS, DE and I2S Audio Supported
- Up to 4 I2S Digital Audio Inputs for Surround
Sound Applications - 4 Bidirectional GPIO Channels with 2 Dedicated
Pins - Single 3.3-V Supply with 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface - AC-Coupled STP Interconnect up to 10 Meters
- DC-Balanced & Scrambled Data with Embedded
Clock - Supports HDCP Repeater Application
- Internal Pattern Generation
- Low Power Modes Minimize Power Dissipation
- Automotive Grade Product: AEC-Q100 Grade 2
Qualified - > 8-kV HBM and ISO 10605 ESD Rating
- Backward Compatible Modes
The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
お客様が関心を持ちそうな類似品
比較対象デバイスと同等の機能で、ピン互換製品。
比較対象デバイスと類似の機能。
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | DS90UH927Q-Q1 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP データシート (Rev. C) | PDF | HTML | 2015/02/02 | ||
| アプリケーション・ノート | Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices | 2013/05/04 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
DS90UH927QEVM — DS90UH927Q-Q1 5MHz-85MHz FPD-Link III シリアライザ評価モジュール
The Texas Instruments DS90UB927QEVM evaluation module (EVM) helps system designers evaluate the operation and performance of the DS90UB927Q 5MHz-85MHz FPD-Link III Serializer (SER). The device translates four FPD-Link (I) compatible LVDS data input pairs and one LVDS clock into a high-speed (...)
ALP — Analog LaunchPad Framework Utility
ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |
購入と品質
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。