홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 멀티미디어 및 산업용 네트워킹 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
멀티미디어 및 산업용 네트워킹 SoC

AM3351

활성

Sitara 프로세서: ARM Cortex-A8, 1Gb 이더넷, 디스플레이

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AM3351

활성
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CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600 Display type 1 LCD Protocols Ethernet Hardware accelerators Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600 Display type 1 LCD Protocols Ethernet Hardware accelerators Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
NFBGA (ZCE) 298 169 mm² 13 x 13
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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상위 문서 유형 직함 형식 옵션 날짜
* Data sheet AM335x Sitara™ Processors datasheet (Rev. L) PDF | HTML 2019/11/15
* Errata AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 2017/01/03
* User guide AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2023/02/14
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2026/02/12
Application note HSR/PRP Solutions on Sitara Processors for Grid Substation Communication (Rev. A) PDF | HTML 2026/01/30
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025/11/24
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025/02/26
Application note Basic Ethernet Interface Debug With Linux PDF | HTML 2024/10/11
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 2023/07/31
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023/05/24
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/02/24
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022/10/11
Design guide Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) PDF | HTML 2021/11/09
Application note nfBGA Packaging (Rev. C) PDF | HTML 2021/05/17
Application note Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 2021/05/07
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020/12/16
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020/07/28
User guide Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B) 2020/02/27
Application note AM335x EMIF Tools 2019/09/20
Application note AM335x PMIC Selection Guide (Rev. A) 2019/09/19
Application note Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019/09/13
Product overview Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 2019/07/30
White paper Power optimization techniques for energy-efficient systems (Rev. A) 2019/06/28
Application note Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019/05/07
Application note AM335x Hardware Design Guide PDF | HTML 2019/05/03
Application note How to Port WOLFSSL Onto TI Sitara AM335 Starter Kit PDF | HTML 2019/04/24
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 2019/04/11
Application note Common EOS pitfalls in board design 2019/02/13
Application note PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019/01/18
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 2019/01/10
Application note PRU Read Latencies (Rev. A) 2018/12/21
Application note PRU-ICSS Getting Starting Guide on Linux (Rev. A) 2018/12/10
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018/11/07
Application note PRU-ICSS / PRU_ICSSG Migration Guide 2018/11/05
White paper Secure Boot on embedded Sitara™ processors (Rev. A) 2018/10/13
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/09/24
Application note Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 2018/03/28
User guide Powering the AM335x With the TPS650250 (Rev. B) 2018/03/14
White paper Data concentrators: The core of energy and data management (Rev. A) 2018/02/21
User guide PRU Assembly Instruction User Guide 2018/02/16
White paper POWERLINK on TI Sitara Processors (Rev. A) 2018/01/10
White paper Achieving increased functionality and efficiency in vacuum robots 2017/12/21
Product overview TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 2017/12/19
User guide TPS65910Ax User's Guide for AM335x Processors (Rev. F) 2017/12/08
Technical article Introduction to EV charging displays PDF | HTML 2017/11/15
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/08/14
Application note Processor-SDK RTOS Power Management and Measurement 2017/08/02
Application note Sitara Linux ALSA DSP Microphone Array Voice Recognition 2017/06/30
Application note AM335x Reliability Considerations in PLC Applications (Rev. A) 2017/04/27
Application note AM335x Low Power Design Guide (Rev. A) 2017/02/28
White paper Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016/08/11
Technical article Announcing the new entry-level Sitara processor PDF | HTML 2015/12/09
White paper Building automation for enhanced energy and operational efficiency (Rev. A) 2015/10/26
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015/08/13
White paper Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 2015/03/03
User guide G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 2014/11/13
User guide Powering the AM335x with the TPS65217x . (Rev. I) 2014/09/06
Application note AM335x and AM43xx Sitara Processors USB Layout Guidelines (Rev. A) 2014/08/21
White paper Mainline Linux™ ensures stability and innovation 2014/03/27
White paper Linaro Speeds Development in TI Linux SDKs 2013/08/27
White paper The Yocto Project:Changing the way embedded Linux software solutions are develop 2013/03/14
White paper Smart thermostats are a cool addition to the connected home 2012/09/27

설계 및 개발

전원 공급 솔루션

AM3351에 사용 가능한 전원 공급 솔루션을 찾아보세요. TI는 칩(SoC), 프로세서, 마이크로컨트롤러, 센서 또는 FPGA(Field Programmable Gate Array)의 TI와 비TI 시스템을 위한 전원 공급 솔루션을 제공합니다.

솔루션 보기
평가 보드

TMDXEVM3358 — AM335x 평가 모듈

The AM335x Evaluation Module (EVM) enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications for factory automation, building automation, grid infrastructure, and more.

사용 설명서: PDF
TI.com에서 구매할 수 없음
평가 보드

TPS65217CEVM — TPS65217C 평가 모듈

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

사용 설명서: PDF
TI.com에서 구매할 수 없음
평가 보드

TPS65218EVM-100 — TPS65218 평가 모듈

The TPS65218EVM is a fully assembled platform for evaluating the performance of the TPS65218 power management device.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없음
평가 보드

ADVAN-3P-SITARA-SOMS — Advantech Sitara SOM 및 SBC

Advantech offers Sitara™ based embedded core computing solutions including computer-on-modules, single-board-computers and box computers. Their compact, low-power-consumption, and cost-effective Arm®-based platform solutions are designed to deliver easier system integration, better (...)
발송: Advantech
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평가 보드

BEAGL-BONE-GRN-ECO — Seeed Studio BeagleBone® Green eco 평가 모듈

Seeed Studio BeagleBone® Green Eco는 AM335x Arm® Cortex®-A8 프로세서를 탑재한 저렴한 비용의 산업용 등급 오픈 소스 하드웨어 개발 플랫폼입니다. 이 4계층 설계에는 더 넓은 온도 범위, 향상된 전력 안정성, 향상된 eMMC(Embedded MultiMediaCard) 스토리지, 상용 및 산업용 애플리케이션을 위해 설계된 기가비트 이더넷을 지원하는 고품질 부품이 내장되어 있습니다. 이 보드는 BeagleBoard.org와의 파트너십을 통해 개발된 Seeed Studio (...)
발송: Seeed Technology Co., Ltd.
사용 설명서: PDF | HTML
TI.com에서 구매할 수 없음
평가 보드

BYTES-3P-SITARASOMS — bytes at work Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


발송: bytes at work AG
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평가 보드

COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
발송: CompuLab
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평가 보드

CRLNK-3P-SOMS — Critical Link system on modules for TI ARM-based Processors

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

발송: Critical Link LLC
파트너 사이트 방문
평가 보드

FORLX-3P-SITARA-SOMS — Forlinx Sitara SOM

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
발송: Forlinx Embedded Tech. Co., Ltd
파트너 사이트 방문
평가 보드

MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
발송: MYIR Tech Limited
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평가 보드

OCTVO-3P-AM335X — Octavo 시스템 AM335x 기반 시스템-인-패키지

Octavo Systems는 전 세계의 혁신가에게 SIP(System-in-Package) 기반 솔루션을 제공하는 선도 기업입니다. SIP 장치로 구성된 OSD335x 제품군은 텍사스 인스트루먼트의 Sitara™ AM335x Arm® Cortex®-A8 프로세서 기반의 고성능 임베디드 시스템을 개발하고 배포할 수 있는 가장 빠르고 경제적인 방법입니다.

OSD335x 장치는 최대 1GHz로 실행되는 Sitara™ AM335x Arm® Cortex®-A8 프로세서와 최대 1GB의 DDR3, TPS65217C 전력 관리 IC, (...)

발송: Octavo Systems
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평가 보드

PHYTC-3P-PHYBOARD-AM335X — AM335x Arm® 기반 Sitara™ 프로세서용 PHYTEC® phyBOARD® -AM335x 개발 키트

phyBOARD®-AM335x는 캐리어 보드 PCB에 직접 납땜되는 TI Sitara™ AM335x를 기반으로 하는 phyCORE-AM335x SOM(System On Module)을 갖추고 있습니다. 캐리어 보드에 대한 SOM의 이 "DSC(직접 납땜 연결)" 방식은 보드 간 커넥터를 제거하여 시스템 비용을 줄입니다. Pico-ITX 폼 팩터에서 phyBOARD는 광범위한 강력한 산업 응용 제품에 배포하는 데 이상적입니다.

PHYTEC는 고객이 복잡한 제품을 빠르고 쉽게 시장에 출시할 수 있도록 지원하는 SOM(System on (...)

발송: PHYTEC
파트너 사이트 방문
평가 보드

PHYTC-3P-PHYCORE-AM335X — PHYTEC phyCORE-AM335x 시스템 온 모듈

phyCORE®-AM335x SOM은 높은 처리 성능, 저전력, 최첨단 그래픽 처리 및 실시간 프로토콜 지원으로 강화된 고집적 주변 장치 세트를 갖춘 텍사스 인스트루먼트 Sitara™ AM335x 프로세서 제품군을 지원합니다. 220핀 SOM 상호 연결을 통해 듀얼 USB OTG, 듀얼 기가비트 이더넷, CAN 및 LCD와 같은 인터페이스에 쉽게 액세스할 수 있습니다.

PHYTEC는 고객이 복잡한 제품을 빠르고 쉽게 시장에 출시할 수 있도록 지원하는 SOM(System on Modules), 임베디드 미들웨어 및 설계 서비스의 업계 (...)

발송: PHYTEC
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평가 보드

TQ-3P-SITARASOMS — TQ Group Sitara SOM

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
발송: TQ-Group
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평가 보드

VANWS-3P-VGATEWAY — AM335x 기반 Vanteon Wireless Solutions의 vGATEWAY 레퍼런스 설계

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

발송: Vanteon Wireless Solutions
파트너 사이트 방문
평가 보드

VAR-3P-SITARASOMS — Variscite Sitara SOM

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
발송: Variscite
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도터 카드

WL1837MODCOM8I — WiLink™ 8 듀얼 밴드 2.4 및 5GHz Wi-Fi® + Bluetooth® COM8 평가 모듈

TI WiLink™ 8 module family The WL1837MODCOM8I is one of the two evaluation boards for the TI WiLink™ 8 combo module family. For designs requiring performance in the 2.4 GHz band only, see the WL1835MODCOM8.

The WL1837MODCOM8I, which is compatible with many processors including TI’s (...)

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

XDS200은 TI 20핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매할 수 없음
디버그 프로브

LB-3P-TRACE32-ARM — Arm® 기반 마이크로컨트롤러 및 프로세서용 Lauterbach TRACE32® 디버그 및 트레이스 시스템

Lauterbach의 TRACE32® 툴은 개발자가 모든 종류의 Arm® 기반 마이크로컨트롤러 및 프로세서를 분석, 최적화 및 인증할 수 있도록 하는 첨단 하드웨어 및 소프트웨어 구성 요소 제품군입니다. 세계적으로 유명한 임베디드 시스템 및 SoC용 디버그 및 트레이스 솔루션은 초기 사전 실리콘 개발부터 현장의 제품 인증 및 문제 해결에 이르기까지 모든 개발 단계를 위한 완벽한 솔루션입니다. Lauterbach 툴의 직관적인 모듈형 설계는 엔지니어에게 현존하는 최고의 성능을 제공하고 요구 사항 변화에 따라 적응하고 성장하는 (...)

발송: Lauterbach GmbH
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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM335X — Linux Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-AM335X — Linux-RT Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-RTOS-AM335X — TI-RTOS Processor SDK for AM335x and AMIC110 devices (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
드라이버 또는 라이브러리

TI-15.4-STACK-GATEWAY-LINUX-SDK — TI 15.4-Stack 게이트웨이 Linux 소프트웨어 개발 키트

The TI-15.4-Stack-Gateway-Linux Software Development Kit (SDK) provides a Linux software middleware for the TI 15.4-Stack companion solution. It includes a full Linux user-space software that runs on top of the TI Processor SDK for AM335x platform, which interfaces with the co-processor embedded (...)
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드라이버 또는 라이브러리

WIND-3P-VXWORKS-LINUX-OS — Wind River 프로세서 VxWorks 및 Linux 운영 체제

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
발송: Wind River Systems
파트너 사이트 방문
드라이버 또는 라이브러리

WIT-3P-SITARABSP — Witekio Sitara Android 및 Windows 운영 체제

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
발송: Witekio
파트너 사이트 방문
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
운영 체제(OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
발송: Green Hills Software
파트너 사이트 방문
운영 체제(OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
발송: Mentor Graphics Corporation
파트너 사이트 방문
소프트웨어 프로그래밍 도구

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드
소프트웨어 프로그래밍 도구

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is part of TI's extensive CCStudio™ development ecosystem and is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces and can be run on (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
시뮬레이션 모델

AM335x Thermal Model

SPRM824.ZIP (10 KB) - Thermal Model
다운로드
시뮬레이션 모델

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS Model
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시뮬레이션 모델

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL Model
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시뮬레이션 모델

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL Model
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계산 툴

CLOCKTREETOOL — Sitara, 오토모티브, 비전 분석 및 디지털 신호 프로세서용 클록 트리 툴

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
사용 설명서: PDF
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계산 툴

POWEREST — 전력 예상 툴(PET)

PET(전력 예상 툴)은 사용자가 일부 TI 프로세서의 소비 전력에 대한 인사이트를 얻게 해줍니다. 이 툴에는 사용자가 여러 가지 애플리케이션 시나리오를 선택하여 소비 전력뿐 아니라, 전체 소비 전력을 더 줄이기 위해 고급 전력 절약 기법을 적용하는 방법을 파악할 수 있는 기능이 포함되어 있습니다.
AM57x 및 AM437x 프로세서용 PET:

이 다운로드 가능한 스프레드시트는 사용자가 애플리케이션에 필요한 장치 매개 변수를 입력하는 메커니즘입니다. 매개 변수로는 IP 활동/로딩, 원하는 전력 상태 및 전력 관리 사용량 등이 (...)

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계산 툴

SITARA-DDR-CONFIG-TOOL — Sitara EMIF(외부 메모리 인터페이스) 툴

Sitara™ EMIF 툴은 외부 DDR 메모리 장치에 액세스하기 위해 TI 프로세서를 구성하는 인터페이스를 제공하는 소프트웨어 툴입니다. 또한 이 툴은 보드 라우팅 스큐를 보상하도록 DLL(Delay Locked Loop) 설정을 최적화합니다. 결과는 EMIF 구성 레지스터로 출력되며, 이를 가져와서 프로세서 SDK, Code Composer Studio 또는 사용자 지정 소프트웨어에서 사용할 수 있습니다.  
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계산 툴

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF Tool Spreadsheet

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드
레퍼런스 디자인

TIDEP-0087 — EV 충전 인프라용 HMI(Human Machine Interface) 레퍼런스 디자인

이 프로세서 기반 레퍼런스 설계는 시장 출시 시기를 앞당기고, 고객이 EV(전기 자동차) 충전 인프라 또는 EVSE(EV 전원 공급 장비)를 위한 비용 효율적인 HMI(Human Machine Interface) 솔루션을 설계하는 데 도움이 됩니다. 이 레퍼런스 설계는 소프트웨어 렌더링 그래픽을 위한 TI 프로세서 기능과 함께 EVSE HMI에 일반적으로 사용되는 2D(2차원) Qt GUI(그래픽 사용자 인터페이스)를 보여줍니다. AM335x 프로세서는 다양한 프로세싱 속도, 저가형 애플리케이션을 위한 호환 가능한 소프트웨어, (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP-01005 — 스마트 온도 조절기용 HMI(인간-기계 인터페이스) 레퍼런스 설계

이 프로세서 기반 레퍼런스 설계는 시장 출시 기간을 단축하고 고객이 스마트 서모스탯을 위한 비용 효율적인 HMI(Human-Machine Interface) 솔루션을 설계할 수 있도록 지원합니다. Sitara™ AM335x 프로세서 제품군은 300MHz~1GHz의 처리 속도, 그래픽 가속화, 로우엔드부터 하이엔드 애플리케이션을 충족하는 소프트웨어, UART(범용 비동기 리시버/트랜스미터), SDIO, USB 등과 같은 스마트 서모스탯 HMI에 필요한 주요 주변 기기를 통한 충분한 연결 기능을 갖춘 확장 가능한 대안을 제공합니다.

이 (...)

Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP-0102 — 보호 릴레이용 HMI(Human Machine Interface) 레퍼런스 디자인

이 프로세서 기반 레퍼런스 설계는 시장 출시 기간을 단축하고 고객이 보호 릴레이를 위한 비용 효율적인 HMI(Human-Machine Interface) 솔루션을 설계할 수 있도록 지원합니다. 이 레퍼런스 설계는 소프트웨어 렌더링 그래픽을 위한 TI 프로세서 기능과 함께 보호 릴레이 HMI에 일반적으로 사용되는 2차원(2D) Qt 그래픽 사용자 인터페이스(GUI)를 보여줍니다. AM335x 프로세서는 다양한 처리 속도를 제공하고 동일한 소프트웨어 개발 환경을 사용하여 저사양은 물론 고사양 애플리케이션까지 만족시키는 확장성을 제공할 (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0019 — Beaglebone 케이프 및 시작 키트의 IEC 61850 변전소 베이 컨트롤러 데모

BeagleBone 케이프/시작 키트의 변전소 베이 컨트롤러 IEC 61850 변전소 베이 컨트롤러의 경제적이고 간소한 구현으로 Triangle MicroWorks IEC 61850 스택을 Linux 대상 계층 정의를 사용하여 TI AM335X 플랫폼에서 효율적으로 실행할 수 있습니다. AM335X 플랫폼 및 61850 스택 데모에 기반을 둔 다양한 변전소 자동화 애플리케이션을 구축할 수 있습니다.
Design guide: PDF
회로도: PDF
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NFBGA (ZCE) 298 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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