DSLVDS1048

現行

3.3V LVDS 四通道高速差分線路接收器

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Designed for Signal Rates up to 400 Mbps
  • Flow-Through Pinout Simplifies PCB Layout
  • 150-ps Channel-to-Channel Skew (Typical)
  • 100-ps Differential Skew (Typical)
  • 2.7-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low Power Design (40 mW at 3.3-V Static)
  • Interoperable With Existing 5-V LVDS Drivers
  • Accepts Small Swing (350 mV Typical) Differential Signal Levels
  • Supports Input Failsafe
    • Open, Short, and Terminated
  • 0 V to −100 mV Threshold Region
  • Operating Temperature Range: –40°C to +85°C
  • Meets or Exceeds ANSI/TIA/EIA-644 Standard
  • Available in TSSOP Package
  • Designed for Signal Rates up to 400 Mbps
  • Flow-Through Pinout Simplifies PCB Layout
  • 150-ps Channel-to-Channel Skew (Typical)
  • 100-ps Differential Skew (Typical)
  • 2.7-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low Power Design (40 mW at 3.3-V Static)
  • Interoperable With Existing 5-V LVDS Drivers
  • Accepts Small Swing (350 mV Typical) Differential Signal Levels
  • Supports Input Failsafe
    • Open, Short, and Terminated
  • 0 V to −100 mV Threshold Region
  • Operating Temperature Range: –40°C to +85°C
  • Meets or Exceeds ANSI/TIA/EIA-644 Standard
  • Available in TSSOP Package

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

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DSLVDS1047 現行 3.3V LVDS 四通道高速差分線路驅動器 Driver variant

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DSLVDS1048 3.3-V LVDS Quad Channel High-Speed Differential Line Receiver datasheet PDF | HTML 2018/9/27
應用說明 Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 2020/10/29
應用說明 Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners 2019/6/29
Application brief LVDS to Improve EMC in Motor Drives 2018/9/27
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018/8/3
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018/5/16
應用說明 An Overview of LVDS Technology 1998/10/5

設計與開發

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開發板

DSLVDS1047-1048EVM — 四通道 LVDS 驅動器和接收器評估模組

DSLVDS1047-1048EVM 評估模組 (EVM) 專為德州儀器 DSLVDS1047 3-V LVDS 四路 CMOS 差動線路驅動器和 DSLVDS1048 3-V LVDS CMOS 差動線路接收器的性能與功能評估而設計。使用者可運用此套件快速評估 DSLVDS1047 和 DSLVDS1048 支援的輸出波形特性和訊號完整性。接頭針腳可連接至 DSLVDS1047 和 DSLVDS1048 輸入及輸出,也便於連接至實驗室設備或使用者系統,以進行性能評估。
使用指南: PDF
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子卡

TMDSFSIADAPEVM — 快速序列介面 (FSI) 轉接板評估模組

更快、更平價、更穩固:透過全新序列通訊技術在隔離中實現 200 Mbps 的傳輸量——快速序列介面 (FSI)

FSI 是一種低訊號計數序列通訊週邊設備,可在 C2000 即時控制微控制器 (MCU) 上使用,與其他序列週邊設備相比,可提供低成本、可靠的通訊及更高速的傳輸量,最高可達 200 Mbps。FSI 能在低延遲裝置間傳遞時間關鍵資料,因此可實現新拓撲結構與方法,並在控制系統內分散處理、感測與致動。FSI 設計為搭配隔離裝置使用,可在系統的「熱」(高電壓)側和「冷」(低電壓)側之間提供高速通訊。

FSI 轉接器電路板是一款評估板,可協助理解 C2000 FSI (...)

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模擬型號

DSLVDS1048 IBIS Model

SNLM223.ZIP (8 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 16 Ultra Librarian

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