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LVDS、M-LVDS 和 PECL IC

DSLVDS1048

現行

3.3V LVDS 四通道高速差分線路接收器

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產品規格表

DSLVDS1048

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Designed for Signal Rates up to 400 Mbps
  • Flow-Through Pinout Simplifies PCB Layout
  • 150-ps Channel-to-Channel Skew (Typical)
  • 100-ps Differential Skew (Typical)
  • 2.7-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low Power Design (40 mW at 3.3-V Static)
  • Interoperable With Existing 5-V LVDS Drivers
  • Accepts Small Swing (350 mV Typical) Differential Signal Levels
  • Supports Input Failsafe
    • Open, Short, and Terminated
  • 0 V to −100 mV Threshold Region
  • Operating Temperature Range: –40°C to +85°C
  • Meets or Exceeds ANSI/TIA/EIA-644 Standard
  • Available in TSSOP Package
  • Designed for Signal Rates up to 400 Mbps
  • Flow-Through Pinout Simplifies PCB Layout
  • 150-ps Channel-to-Channel Skew (Typical)
  • 100-ps Differential Skew (Typical)
  • 2.7-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low Power Design (40 mW at 3.3-V Static)
  • Interoperable With Existing 5-V LVDS Drivers
  • Accepts Small Swing (350 mV Typical) Differential Signal Levels
  • Supports Input Failsafe
    • Open, Short, and Terminated
  • 0 V to −100 mV Threshold Region
  • Operating Temperature Range: –40°C to +85°C
  • Meets or Exceeds ANSI/TIA/EIA-644 Standard
  • Available in TSSOP Package

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.
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類型 標題 日期
* Data sheet DSLVDS1048 3.3-V LVDS Quad Channel High-Speed Differential Line Receiver datasheet PDF | HTML 2018年 9月 27日
Application note Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 2020年 10月 29日
Application note Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners 2019年 6月 29日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
Application note An Overview of LVDS Technology 1998年 10月 5日

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開發板

DSLVDS1047-1048EVM — 四通道 LVDS 驅動器和接收器評估模組

The DSLVDS1047-1048EVM is an evaluation module (EVM) designed for performance and functional evaluation of the Texas Instruments DSLVDS1047 3-V LVDS Quad CMOS Differential Line Driver and DSLVDS1048 3-V LVDS CMOS Differential Line Receiver. With this kit, users can quickly evaluate the output (...)
使用指南: PDF
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TMDSFSIADAPEVM — 快速序列介面 (FSI) 轉接板評估模組

Faster, cheaper, more robust: achieve 200 Mbps throughput across isolation with new serial communication technology – Fast Serial Interface (FSI)

FSI is a low signal count serial communications peripheral, available on C2000 Real-Time Control Microcontrollers (MCU), which offers low-cost reliable (...)

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模擬型號

DSLVDS1048 IBIS Model

SNLM223.ZIP (8 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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